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List: qemu-devel
Subject: Re: [PATCH 1/3] target/hppa: Squash d for pa1.x during decode
From: Helge Deller <deller () gmx ! de>
Date: 2024-03-26 9:46:13
Message-ID: 11ad662e-1da3-4061-b39c-4a289d151852 () gmx ! de
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On 3/26/24 07:44, Richard Henderson wrote:
> The cond_need_ext predicate was created while we still had a
> 32-bit compilation mode. It now makes more sense to treat D
> as an absolute indicator of a 64-bit operation.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Helge Deller <deller@gmx.de>
Tested-by: Helge Deller <deller@gmx.de>
Helge
> ---
> target/hppa/insns.decode | 20 +++++++++++++-------
> target/hppa/translate.c | 38 ++++++++++++++++++++------------------
> 2 files changed, 33 insertions(+), 25 deletions(-)
>
> diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
> index f58455dfdb..6a74cf23cd 100644
> --- a/target/hppa/insns.decode
> +++ b/target/hppa/insns.decode
> @@ -57,6 +57,9 @@
> %neg_to_m 0:1 !function=neg_to_m
> %a_to_m 2:1 !function=neg_to_m
> %cmpbid_c 13:2 !function=cmpbid_c
> +%d_5 5:1 !function=pa20_d
> +%d_11 11:1 !function=pa20_d
> +%d_13 13:1 !function=pa20_d
>
> ####
> # Argument set definitions
> @@ -84,15 +87,16 @@
> # Format definitions
> ####
>
> -@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d
> +@rr_cf_d ...... r:5 ..... cf:4 ...... . t:5 &rr_cf_d d=%d_5
> @rrr ...... r2:5 r1:5 .... ....... t:5 &rrr
> @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
> -@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
> +@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d d=%d_5
> @rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh
> -@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh
> -@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0
> +@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_d_sh d=%d_5
> +@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d_sh d=%d_5 sh=0
> @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
> -@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11
> +@rri_cf_d ...... r:5 t:5 cf:4 . ........... \
> + &rri_cf_d d=%d_11 i=%lowsign_11
>
> @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \
> &rrb_c_f disp=%assemble_12
> @@ -368,8 +372,10 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
> # Conditional Branches
> ####
>
> -bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
> -bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
> +bb_sar 110000 00000 r:5 c:1 1 . ........... n:1 . \
> + disp=%assemble_12 d=%d_13
> +bb_imm 110001 p:5 r:5 c:1 1 . ........... n:1 . \
> + disp=%assemble_12 d=%d_13
>
> movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
> movbi 110011 ..... ..... ... ........... . . @rib_cf f=0
> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
> index 99c5c4cbca..a70d644c0b 100644
> --- a/target/hppa/translate.c
> +++ b/target/hppa/translate.c
> @@ -200,6 +200,14 @@ static int cmpbid_c(DisasContext *ctx, int val)
> return val ? val : 4; /* 0 == "*<<" */
> }
>
> +/*
> + * In many places pa1.x did not decode the bit that later became
> + * the pa2.0 D bit. Suppress D unless the cpu is pa2.0.
> + */
> +static int pa20_d(DisasContext *ctx, int val)
> +{
> + return ctx->is_pa20 & val;
> +}
>
> /* Include the auto-generated decoder. */
> #include "decode-insns.c.inc"
> @@ -693,12 +701,6 @@ static bool cond_need_cb(int c)
> return c == 4 || c == 5;
> }
>
> -/* Need extensions from TCGv_i32 to TCGv_i64. */
> -static bool cond_need_ext(DisasContext *ctx, bool d)
> -{
> - return !(ctx->is_pa20 && d);
> -}
> -
> /*
> * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
> * the Parisc 1.1 Architecture Reference Manual for details.
> @@ -715,7 +717,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
> cond = cond_make_f();
> break;
> case 1: /* = / <> (Z / !Z) */
> - if (cond_need_ext(ctx, d)) {
> + if (!d) {
> tmp = tcg_temp_new_i64();
> tcg_gen_ext32u_i64(tmp, res);
> res = tmp;
> @@ -725,7 +727,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
> case 2: /* < / >= (N ^ V / !(N ^ V) */
> tmp = tcg_temp_new_i64();
> tcg_gen_xor_i64(tmp, res, sv);
> - if (cond_need_ext(ctx, d)) {
> + if (!d) {
> tcg_gen_ext32s_i64(tmp, tmp);
> }
> cond = cond_make_0_tmp(TCG_COND_LT, tmp);
> @@ -742,7 +744,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
> */
> tmp = tcg_temp_new_i64();
> tcg_gen_eqv_i64(tmp, res, sv);
> - if (cond_need_ext(ctx, d)) {
> + if (!d) {
> tcg_gen_sextract_i64(tmp, tmp, 31, 1);
> tcg_gen_and_i64(tmp, tmp, res);
> tcg_gen_ext32u_i64(tmp, tmp);
> @@ -760,13 +762,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
> tmp = tcg_temp_new_i64();
> tcg_gen_neg_i64(tmp, cb_msb);
> tcg_gen_and_i64(tmp, tmp, res);
> - if (cond_need_ext(ctx, d)) {
> + if (!d) {
> tcg_gen_ext32u_i64(tmp, tmp);
> }
> cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
> break;
> case 6: /* SV / NSV (V / !V) */
> - if (cond_need_ext(ctx, d)) {
> + if (!d) {
> tmp = tcg_temp_new_i64();
> tcg_gen_ext32s_i64(tmp, sv);
> sv = tmp;
> @@ -827,7 +829,7 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d,
> if (cf & 1) {
> tc = tcg_invert_cond(tc);
> }
> - if (cond_need_ext(ctx, d)) {
> + if (!d) {
> TCGv_i64 t1 = tcg_temp_new_i64();
> TCGv_i64 t2 = tcg_temp_new_i64();
>
> @@ -904,7 +906,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d,
> g_assert_not_reached();
> }
>
> - if (cond_need_ext(ctx, d)) {
> + if (!d) {
> TCGv_i64 tmp = tcg_temp_new_i64();
>
> if (ext_uns) {
> @@ -979,7 +981,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res)
> static TCGv_i64 get_carry(DisasContext *ctx, bool d,
> TCGv_i64 cb, TCGv_i64 cb_msb)
> {
> - if (cond_need_ext(ctx, d)) {
> + if (!d) {
> TCGv_i64 t = tcg_temp_new_i64();
> tcg_gen_extract_i64(t, cb, 32, 1);
> return t;
> @@ -3448,12 +3450,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
>
> tmp = tcg_temp_new_i64();
> tcg_r = load_gpr(ctx, a->r);
> - if (cond_need_ext(ctx, a->d)) {
> + if (a->d) {
> + tcg_gen_shl_i64(tmp, tcg_r, cpu_sar);
> + } else {
> /* Force shift into [32,63] */
> tcg_gen_ori_i64(tmp, cpu_sar, 32);
> tcg_gen_shl_i64(tmp, tcg_r, tmp);
> - } else {
> - tcg_gen_shl_i64(tmp, tcg_r, cpu_sar);
> }
>
> cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
> @@ -3470,7 +3472,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
>
> tmp = tcg_temp_new_i64();
> tcg_r = load_gpr(ctx, a->r);
> - p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0);
> + p = a->p | (a->d ? 0 : 32);
> tcg_gen_shli_i64(tmp, tcg_r, p);
>
> cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
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