From qemu-devel Tue Mar 26 09:46:13 2024 From: Helge Deller Date: Tue, 26 Mar 2024 09:46:13 +0000 To: qemu-devel Subject: Re: [PATCH 1/3] target/hppa: Squash d for pa1.x during decode Message-Id: <11ad662e-1da3-4061-b39c-4a289d151852 () gmx ! de> X-MARC-Message: https://marc.info/?l=qemu-devel&m=171144629027044 On 3/26/24 07:44, Richard Henderson wrote: > The cond_need_ext predicate was created while we still had a > 32-bit compilation mode. It now makes more sense to treat D > as an absolute indicator of a 64-bit operation. > > Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Tested-by: Helge Deller Helge > --- > target/hppa/insns.decode | 20 +++++++++++++------- > target/hppa/translate.c | 38 ++++++++++++++++++++------------------ > 2 files changed, 33 insertions(+), 25 deletions(-) > > diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode > index f58455dfdb..6a74cf23cd 100644 > --- a/target/hppa/insns.decode > +++ b/target/hppa/insns.decode > @@ -57,6 +57,9 @@ > %neg_to_m 0:1 !function=3Dneg_to_m > %a_to_m 2:1 !function=3Dneg_to_m > %cmpbid_c 13:2 !function=3Dcmpbid_c > +%d_5 5:1 !function=3Dpa20_d > +%d_11 11:1 !function=3Dpa20_d > +%d_13 13:1 !function=3Dpa20_d > > #### > # Argument set definitions > @@ -84,15 +87,16 @@ > # Format definitions > #### > > -@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d > +@rr_cf_d ...... r:5 ..... cf:4 ...... . t:5 &rr_cf_d d=3D%d= _5 > @rrr ...... r2:5 r1:5 .... ....... t:5 &rrr > @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf > -@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d > +@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d d=3D%= d_5 > @rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh > -@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh > -@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh= =3D0 > +@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_d_sh d= =3D%d_5 > +@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d_sh d= =3D%d_5 sh=3D0 > @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=3D%l= owsign_11 > -@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=3D%= lowsign_11 > +@rri_cf_d ...... r:5 t:5 cf:4 . ........... \ > + &rri_cf_d d=3D%d_11 i=3D%lowsign_11 > > @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ > &rrb_c_f disp=3D%assemble_12 > @@ -368,8 +372,10 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..= ... @mpyadd > # Conditional Branches > #### > > -bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=3D%as= semble_12 > -bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=3D%as= semble_12 > +bb_sar 110000 00000 r:5 c:1 1 . ........... n:1 . \ > + disp=3D%assemble_12 d=3D%d_13 > +bb_imm 110001 p:5 r:5 c:1 1 . ........... n:1 . \ > + disp=3D%assemble_12 d=3D%d_13 > > movb 110010 ..... ..... ... ........... . . @rrb_cf f=3D0 > movbi 110011 ..... ..... ... ........... . . @rib_cf f=3D0 > diff --git a/target/hppa/translate.c b/target/hppa/translate.c > index 99c5c4cbca..a70d644c0b 100644 > --- a/target/hppa/translate.c > +++ b/target/hppa/translate.c > @@ -200,6 +200,14 @@ static int cmpbid_c(DisasContext *ctx, int val) > return val ? val : 4; /* 0 =3D=3D "*<<" */ > } > > +/* > + * In many places pa1.x did not decode the bit that later became > + * the pa2.0 D bit. Suppress D unless the cpu is pa2.0. > + */ > +static int pa20_d(DisasContext *ctx, int val) > +{ > + return ctx->is_pa20 & val; > +} > > /* Include the auto-generated decoder. */ > #include "decode-insns.c.inc" > @@ -693,12 +701,6 @@ static bool cond_need_cb(int c) > return c =3D=3D 4 || c =3D=3D 5; > } > > -/* Need extensions from TCGv_i32 to TCGv_i64. */ > -static bool cond_need_ext(DisasContext *ctx, bool d) > -{ > - return !(ctx->is_pa20 && d); > -} > - > /* > * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of > * the Parisc 1.1 Architecture Reference Manual for details. > @@ -715,7 +717,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned= cf, bool d, > cond =3D cond_make_f(); > break; > case 1: /* =3D / <> (Z / !Z) */ > - if (cond_need_ext(ctx, d)) { > + if (!d) { > tmp =3D tcg_temp_new_i64(); > tcg_gen_ext32u_i64(tmp, res); > res =3D tmp; > @@ -725,7 +727,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned= cf, bool d, > case 2: /* < / >=3D (N ^ V / !(N ^ V) */ > tmp =3D tcg_temp_new_i64(); > tcg_gen_xor_i64(tmp, res, sv); > - if (cond_need_ext(ctx, d)) { > + if (!d) { > tcg_gen_ext32s_i64(tmp, tmp); > } > cond =3D cond_make_0_tmp(TCG_COND_LT, tmp); > @@ -742,7 +744,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned= cf, bool d, > */ > tmp =3D tcg_temp_new_i64(); > tcg_gen_eqv_i64(tmp, res, sv); > - if (cond_need_ext(ctx, d)) { > + if (!d) { > tcg_gen_sextract_i64(tmp, tmp, 31, 1); > tcg_gen_and_i64(tmp, tmp, res); > tcg_gen_ext32u_i64(tmp, tmp); > @@ -760,13 +762,13 @@ static DisasCond do_cond(DisasContext *ctx, unsign= ed cf, bool d, > tmp =3D tcg_temp_new_i64(); > tcg_gen_neg_i64(tmp, cb_msb); > tcg_gen_and_i64(tmp, tmp, res); > - if (cond_need_ext(ctx, d)) { > + if (!d) { > tcg_gen_ext32u_i64(tmp, tmp); > } > cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); > break; > case 6: /* SV / NSV (V / !V) */ > - if (cond_need_ext(ctx, d)) { > + if (!d) { > tmp =3D tcg_temp_new_i64(); > tcg_gen_ext32s_i64(tmp, sv); > sv =3D tmp; > @@ -827,7 +829,7 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsi= gned cf, bool d, > if (cf & 1) { > tc =3D tcg_invert_cond(tc); > } > - if (cond_need_ext(ctx, d)) { > + if (!d) { > TCGv_i64 t1 =3D tcg_temp_new_i64(); > TCGv_i64 t2 =3D tcg_temp_new_i64(); > > @@ -904,7 +906,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsi= gned cf, bool d, > g_assert_not_reached(); > } > > - if (cond_need_ext(ctx, d)) { > + if (!d) { > TCGv_i64 tmp =3D tcg_temp_new_i64(); > > if (ext_uns) { > @@ -979,7 +981,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool= d, TCGv_i64 res) > static TCGv_i64 get_carry(DisasContext *ctx, bool d, > TCGv_i64 cb, TCGv_i64 cb_msb) > { > - if (cond_need_ext(ctx, d)) { > + if (!d) { > TCGv_i64 t =3D tcg_temp_new_i64(); > tcg_gen_extract_i64(t, cb, 32, 1); > return t; > @@ -3448,12 +3450,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_= bb_sar *a) > > tmp =3D tcg_temp_new_i64(); > tcg_r =3D load_gpr(ctx, a->r); > - if (cond_need_ext(ctx, a->d)) { > + if (a->d) { > + tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); > + } else { > /* Force shift into [32,63] */ > tcg_gen_ori_i64(tmp, cpu_sar, 32); > tcg_gen_shl_i64(tmp, tcg_r, tmp); > - } else { > - tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); > } > > cond =3D cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); > @@ -3470,7 +3472,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb= _imm *a) > > tmp =3D tcg_temp_new_i64(); > tcg_r =3D load_gpr(ctx, a->r); > - p =3D a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); > + p =3D a->p | (a->d ? 0 : 32); > tcg_gen_shli_i64(tmp, tcg_r, p); > > cond =3D cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);