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List: kde-commits
Subject: [ktexteditor] /: new hl test infrastructure, using the HTML reporter
From: Christoph Cullmann <cullmann () kde ! org>
Date: 2014-09-09 19:21:56
Message-ID: E1XRQzE-00063E-D5 () scm ! kde ! org
[Download RAW message or body]
Git commit 9c0786f4380bf78dd71a254ae7814e48266653ef by Christoph Cullmann.
Committed on 09/09/2014 at 19:21.
Pushed by cullmann into branch 'master'.
new hl test infrastructure, using the HTML reporter
M +1 -0 autotests/CMakeLists.txt
A +1 -0 autotests/input/syntax/.gitignore
A +32 -0 autotests/input/syntax/dockerfile/results/Dockerfile.reference.html
A +576 -0 autotests/input/syntax/verilog/results/or1200_dc_fsm.v.reference.html
A +1816 -0 autotests/input/syntax/verilog/results/or1200_du.v.reference.html
A +257 -0 autotests/input/syntax/vhdl/results/light52_muldiv.vhdl.reference.html
A +196 -0 autotests/input/syntax/vhdl/results/light52_tb.vhdl.reference.html
A +129 -0 autotests/src/katesyntaxtest.cpp [License: LGPL (v2+)]
A +38 -0 autotests/src/katesyntaxtest.h [License: LGPL (v2+)]
M +3 -11 src/export/exporter.cpp
M +1 -1 src/export/exporter.h
M +10 -2 src/view/kateview.cpp
M +2 -0 src/view/kateview.h
http://commits.kde.org/ktexteditor/9c0786f4380bf78dd71a254ae7814e48266653ef
diff --git a/autotests/CMakeLists.txt b/autotests/CMakeLists.txt
index 90cd643..e16715f 100644
--- a/autotests/CMakeLists.txt
+++ b/autotests/CMakeLists.txt
@@ -123,6 +123,7 @@ ktexteditor_unit_test(commands_test src/script_test_base.cpp \
src/testutils.cpp) ktexteditor_unit_test(scripting_test src/script_test_base.cpp \
src/testutils.cpp) ktexteditor_unit_test(bug313759 src/testutils.cpp)
ktexteditor_unit_test(bug317111 src/testutils.cpp)
+ktexteditor_unit_test(katesyntaxtest)
if (BUILD_VIMODE)
add_subdirectory(src/vimode)
diff --git a/autotests/input/syntax/.gitignore b/autotests/input/syntax/.gitignore
new file mode 100644
index 0000000..704dc35
--- /dev/null
+++ b/autotests/input/syntax/.gitignore
@@ -0,0 +1 @@
+*.current.html
diff --git a/autotests/input/syntax/dockerfile/results/Dockerfile.reference.html \
b/autotests/input/syntax/dockerfile/results/Dockerfile.reference.html new file mode \
100644 index 0000000..7349a7b
--- /dev/null
+++ b/autotests/input/syntax/dockerfile/results/Dockerfile.reference.html
@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "DTD/xhtml1-strict.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
+<meta name="Generator" content="Kate, the KDE Advanced Text Editor" />
+<title>Dockerfile</title>
+</head>
+<body>
+<pre style='color:#1f1c1b;background-color:#ffffff;'>
+<span style='color:#898887;'># LGPLv2+ example file</span>
+
+<span style='color:#898887;'># This is a comment</span>
+<b>FROM</b> ubuntu:14.04
+<b>MAINTAINER</b> James Turnbull <james@example.com> <span \
style='color:#898887;'># comment</span> +<b>ENV</b> REFRESHED_AT 2014-06-01
+
+<b>RUN</b> apt-get -yqq update
+<b>RUN</b> apt-get install -yqq software-properties-common \
python-software-properties +<b>RUN</b> add-apt-repository ppa:chris-lea/redis-server
+<b>RUN</b> apt-get -yqq update
+<b>RUN</b> apt-get -yqq install redis-server redis-tools
+<b>RUN</b> apt-get -yqq update <span style='color:#898887;'># comment</span>
+
+<b>VOLUME</b> [ <span style='color:#bf0303;'>"/var/lib/redis"</span>, \
<span style='color:#bf0303;'>"/var/log/redis/"</span> ] +
+<b>EXPOSE</b> 6379
+
+<b>CMD</b> []
+</pre>
+</body>
+</html>
diff --git a/autotests/input/syntax/verilog/results/or1200_dc_fsm.v.reference.html \
b/autotests/input/syntax/verilog/results/or1200_dc_fsm.v.reference.html new file mode \
100644 index 0000000..664bd2d
--- /dev/null
+++ b/autotests/input/syntax/verilog/results/or1200_dc_fsm.v.reference.html
@@ -0,0 +1,576 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "DTD/xhtml1-strict.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
+<meta name="Generator" content="Kate, the KDE Advanced Text Editor" />
+<title>or1200_dc_fsm.v</title>
+</head>
+<body>
+<pre style='color:#1f1c1b;background-color:#ffffff;'>
+<span style='color:#898887;'>//////////////////////////////////////////////////////////////////////</span>
+<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// OR1200's DC FSM \
////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// This file is part of the OpenRISC \
1200 project ////</span> +<span style='color:#898887;'>//// \
http://opencores.org/project,or1k ////</span> +<span \
style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// Description \
////</span> +<span style='color:#898887;'>//// Data cache state machine \
////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// To Do: \
////</span> +<span style='color:#898887;'>//// - Test error during line read or \
write ////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// Author(s): \
////</span> +<span style='color:#898887;'>//// - Damjan Lampret, \
lampret@opencores.org ////</span> +<span style='color:#898887;'>//// \
- Julius Baxter, julius@opencores.org ////</span> +<span \
style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//////////////////////////////////////////////////////////////////////</span>
+<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// Copyright (C) 2000, 2010 Authors and \
OPENCORES.ORG ////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// This source file may be used and \
distributed without ////</span> +<span style='color:#898887;'>//// \
restriction provided that this copyright statement is not ////</span> +<span \
style='color:#898887;'>//// removed from the file and that any derivative work \
contains ////</span> +<span style='color:#898887;'>//// the original copyright \
notice and the associated disclaimer. ////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// This source file is free software; you \
can redistribute it ////</span> +<span style='color:#898887;'>//// and/or modify it \
under the terms of the GNU Lesser General ////</span> +<span \
style='color:#898887;'>//// Public License as published by the Free Software \
Foundation; ////</span> +<span style='color:#898887;'>//// either version 2.1 of the \
License, or (at your option) any ////</span> +<span style='color:#898887;'>//// \
later version. ////</span> +<span \
style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// This source is distributed in the hope \
that it will be ////</span> +<span style='color:#898887;'>//// useful, but \
WITHOUT ANY WARRANTY; without even the implied ////</span> +<span \
style='color:#898887;'>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \
////</span> +<span style='color:#898887;'>//// PURPOSE. See the GNU Lesser General \
Public License for more ////</span> +<span style='color:#898887;'>//// details. \
////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// You should have received a copy of the \
GNU Lesser General ////</span> +<span style='color:#898887;'>//// Public License \
along with this source; if not, download it ////</span> +<span \
style='color:#898887;'>//// from http://www.opencores.org/lgpl.shtml \
////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//////////////////////////////////////////////////////////////////////</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// $Log: or1200_dc_fsm.v,v $</span>
+<span style='color:#898887;'>// Revision 2.0 2010/06/30 11:00:00 ORSoC</span>
+<span style='color:#898887;'>// Minor update: </span>
+<span style='color:#898887;'>// Bugs fixed. </span>
+<span style='color:#898887;'>//</span>
+
+<span style='color:#898887;'>// synopsys translate_off</span>
+<span style='color:#006e28;'>`include </span><span \
style='color:#b08000;'>"timescale.v"</span> +<span \
style='color:#898887;'>// synopsys translate_on</span> +<span \
style='color:#006e28;'>`include </span><span \
style='color:#b08000;'>"or1200_defines.v"</span> +
+<span style='color:#006e28;'>`define OR1200_DCFSM_IDLE 3'd0</span>
+<span style='color:#006e28;'>`define OR1200_DCFSM_CLOADSTORE 3'd1</span>
+<span style='color:#006e28;'>`define OR1200_DCFSM_LOOP2 3'd2</span>
+<span style='color:#006e28;'>`define OR1200_DCFSM_LOOP3 3'd3</span>
+<span style='color:#006e28;'>`define OR1200_DCFSM_LOOP4 3'd4</span>
+<span style='color:#006e28;'>`define OR1200_DCFSM_FLUSH5 3'd5</span>
+<span style='color:#006e28;'>`define OR1200_DCFSM_INV6 3'd6</span>
+<span style='color:#006e28;'>`define OR1200_DCFSM_WAITSPRCS7 3'd7</span>
+
+
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Data cache FSM for cache line of 16 bytes (4x \
singleword)</span> +<span style='color:#898887;'>//</span>
+
+<b>module</b> or1200_dc_fsm
+ (
+ <span style='color:#898887;'>// Clock and reset</span>
+ clk, rst,
+
+ <span style='color:#898887;'>// Internal i/f to top level DC</span>
+ dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
+ tagcomp_miss, biudata_valid, biudata_error, lsu_addr,
+ dcram_we, biu_read, biu_write, biu_do_sel, dcram_di_sel, first_hit_ack,
+ first_miss_ack, first_miss_err, burst, tag_we, tag_valid, dc_addr,
+ dc_no_writethrough, tag_dirty, dirty, tag, tag_v, dc_block_flush,
+ dc_block_writeback, spr_dat_i, mtspr_dc_done, spr_cswe
+ );
+
+ <span style='color:#898887;'>//</span>
+ <span style='color:#898887;'>// I/O</span>
+ <span style='color:#898887;'>//</span>
+ <span style='color:#0057ae;'>input</span> clk;
+ <span style='color:#0057ae;'>input</span> rst;
+ <span style='color:#0057ae;'>input</span> dc_en;
+ <span style='color:#0057ae;'>input</span> dcqmem_cycstb_i;
+ <span style='color:#0057ae;'>input</span> dcqmem_ci_i;
+ <span style='color:#0057ae;'>input</span> dcqmem_we_i;
+ <span style='color:#0057ae;'>input</span> [<span \
style='color:#b08000;'>3</span>:<span style='color:#b08000;'>0</span>] \
dcqmem_sel_i; + <span style='color:#0057ae;'>input</span> tagcomp_miss;
+ <span style='color:#0057ae;'>input</span> biudata_valid;
+ <span style='color:#0057ae;'>input</span> biudata_error;
+ <span style='color:#0057ae;'>input</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] lsu_addr; \
+ <span style='color:#0057ae;'>output</span> [<span \
style='color:#b08000;'>3</span>:<span style='color:#b08000;'>0</span>] dcram_we; + \
<span style='color:#0057ae;'>output</span> biu_read; + <span \
style='color:#0057ae;'>output</span> biu_write; + <span \
style='color:#0057ae;'>output</span> dcram_di_sel; + <span \
style='color:#0057ae;'>output</span> biu_do_sel; + <span \
style='color:#0057ae;'>output</span> first_hit_ack; + <span \
style='color:#0057ae;'>output</span> first_miss_ack; + <span \
style='color:#0057ae;'>output</span> first_miss_err; + <span \
style='color:#0057ae;'>output</span> burst; + <span \
style='color:#0057ae;'>output</span> tag_we; + <span \
style='color:#0057ae;'>output</span> tag_valid; + <span \
style='color:#0057ae;'>output</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dc_addr; + <span \
style='color:#0057ae;'>input</span> dc_no_writethrough; + <span \
style='color:#0057ae;'>output</span> tag_dirty; + <span \
style='color:#0057ae;'>input</span> dirty; + <span \
style='color:#0057ae;'>input</span> [<span \
style='color:#006e28;'>`OR1200_DCTAG_W</span>-<span \
style='color:#b08000;'>2</span>:<span style='color:#b08000;'>0</span>] tag; + \
<span style='color:#0057ae;'>input</span> tag_v; + <span \
style='color:#0057ae;'>input</span> dc_block_flush; + <span \
style='color:#0057ae;'>input</span> dc_block_writeback; + <span \
style='color:#0057ae;'>input</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] spr_dat_i; + <span \
style='color:#0057ae;'>output</span> mtspr_dc_done; + <span \
style='color:#0057ae;'>input</span> spr_cswe; +
+
+ <span style='color:#898887;'>//</span>
+ <span style='color:#898887;'>// Internal wires and regs</span>
+ <span style='color:#898887;'>//</span>
+ <span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] addr_r; + \
<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>2</span>:<span \
style='color:#b08000;'>0</span>] state; + <span \
style='color:#0057ae;'>reg</span> [<span \
style='color:#006e28;'>`OR1200_DCLS</span>-<span \
style='color:#b08000;'>1</span>:<span style='color:#b08000;'>0</span>] cnt; + \
<span style='color:#0057ae;'>reg</span> hitmiss_eval; + <span \
style='color:#0057ae;'>reg</span> store; + <span \
style='color:#0057ae;'>reg</span> load; + <span \
style='color:#0057ae;'>reg</span> cache_inhibit; + <span \
style='color:#0057ae;'>reg</span> cache_miss; + <span \
style='color:#0057ae;'>reg</span> cache_dirty_needs_writeback; + <span \
style='color:#0057ae;'>reg</span> \
did_early_load_ack; + <span style='color:#0057ae;'>reg</span> \
cache_spr_block_flush; + <span style='color:#0057ae;'>reg</span> \
cache_spr_block_writeback; + <span style='color:#0057ae;'>reg</span> cache_wb; \
+ <span style='color:#0057ae;'>wire</span> load_hit_ack;
+ <span style='color:#0057ae;'>wire</span> load_miss_ack;
+ <span style='color:#0057ae;'>wire</span> load_inhibit_ack;
+ <span style='color:#0057ae;'>wire</span> store_hit_ack;
+ <span style='color:#0057ae;'>wire</span> store_hit_writethrough_ack;
+ <span style='color:#0057ae;'>wire</span> store_miss_writethrough_ack;
+ <span style='color:#0057ae;'>wire</span> store_inhibit_ack;
+ <span style='color:#0057ae;'>wire</span> store_miss_ack;
+ <span style='color:#0057ae;'>wire</span> dcram_we_after_line_load;
+ <span style='color:#0057ae;'>wire</span> dcram_we_during_line_load;
+ <span style='color:#0057ae;'>wire</span> tagram_we_end_of_loadstore_loop;
+ <span style='color:#0057ae;'>wire</span> tagram_dirty_bit_set;
+ <span style='color:#0057ae;'>wire</span> writethrough;
+ <span style='color:#0057ae;'>wire</span> cache_inhibit_with_eval;
+ <span style='color:#0057ae;'>wire</span> [(<span \
style='color:#006e28;'>`OR1200_DCLS</span>-<span \
style='color:#b08000;'>1</span>)-<span style='color:#b08000;'>2</span>:<span \
style='color:#b08000;'>0</span>] next_addr_word; +
+ <span style='color:#898887;'>//</span>
+ <span style='color:#898887;'>// Cache inhibit</span>
+ <span style='color:#898887;'>//</span>
+
+ <span style='color:#898887;'>// Indicates whether cache is inhibited, during \
hitmiss_eval and after</span> + <b>assign</b> cache_inhibit_with_eval = \
(hitmiss_eval & dcqmem_ci_i) | + (!hitmiss_eval & cache_inhibit);
+
+ <span style='color:#898887;'>//</span>
+ <span style='color:#898887;'>// Generate of DCRAM write enables</span>
+ <span style='color:#898887;'>//</span>
+
+ <span style='color:#898887;'>// WE when non-writethrough, and had to wait for a \
line to load.</span> + <b>assign</b> dcram_we_after_line_load = (state == <span \
style='color:#006e28;'>`OR1200_DCFSM_LOOP3</span>) & + dcqmem_we_i & \
!cache_dirty_needs_writeback & + !did_early_load_ack;
+
+ <span style='color:#898887;'>// WE when receiving the data cache line</span>
+ <b>assign</b> dcram_we_during_line_load = (state == <span \
style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span>) & load & + \
biudata_valid; +
+ <b>assign</b> dcram_we =(<span style='color:#898887;'>// Write when hit - make \
sure it is only when hit - could</span> + <span style='color:#898887;'>// maybe \
be doing write through and don't want to corrupt</span> + <span \
style='color:#898887;'>// cache lines corresponding to the writethrough \
addr_r.</span> + ({<span style='color:#b08000;'>4</span>{store_hit_ack | \
store_hit_writethrough_ack}} | + <span style='color:#898887;'>// Write after \
load of line</span> + {<span \
style='color:#b08000;'>4</span>{dcram_we_after_line_load}}) & + \
dcqmem_sel_i ) | + <span style='color:#898887;'>// Write during load</span>
+ {<span style='color:#b08000;'>4</span>{dcram_we_during_line_load}};
+
+ <span style='color:#898887;'>//</span>
+ <span style='color:#898887;'>// Tag RAM signals</span>
+ <span style='color:#898887;'>//</span>
+
+ <span style='color:#898887;'>// WE to tag RAM when we finish loading a \
line.</span> + <b>assign</b> tagram_we_end_of_loadstore_loop = ((state==<span \
style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span>) & + biudata_valid \
& !(|cnt)); +
+<span style='color:#006e28;'>`ifndef OR1200_DC_WRITETHROUGH</span>
+ <span style='color:#898887;'>// No writethrough, so mark a line dirty whenever we \
write to it</span> + <b>assign</b> tagram_dirty_bit_set = store_hit_ack | \
store_miss_ack; +
+ <span style='color:#898887;'>// Generate done signal for MTSPR instructions that \
may block execution</span> + <b>assign</b> mtspr_dc_done = <span \
style='color:#898887;'>// Either DC disabled or we're not selected, or</span> + \
!dc_en | !spr_cswe | + <span style='color:#898887;'>// Requested address not \
valid or writeback and !dirty</span> + ((state==<span \
style='color:#006e28;'>`OR1200_DCFSM_FLUSH5</span>) & + (!tag_v | \
(cache_spr_block_writeback & !dirty))) | + <span style='color:#898887;'>// \
Writeback or flush is finished</span> + ((state==<span \
style='color:#006e28;'>`OR1200_DCFSM_LOOP3</span>) & + \
(cache_spr_block_flush | cache_spr_block_writeback))| + <span \
style='color:#898887;'>// Invalidate of clean line finished</span> + \
((state==<span style='color:#006e28;'>`OR1200_DCFSM_INV6</span>) & \
cache_spr_block_flush); +
+
+<span style='color:#006e28;'>`else</span>
+ <span style='color:#006e28;'>`ifdef</span> OR1200_DC_NOSTACKWRITETHROUGH
+ <span style='color:#898887;'>// For dirty bit setting when having writethrough \
but not for stack</span> + <b>assign</b> tagram_dirty_bit_set = store_hit_ack | \
store_miss_ack; + <span style='color:#006e28;'>`else</span>
+ <span style='color:#898887;'>// Lines will never be dirty if always \
writethrough</span> + <b>assign</b> tagram_dirty_bit_set = <span \
style='color:#b08000;'>0</span>; + <span style='color:#006e28;'>`endif</span>
+
+ <b>assign</b> mtspr_dc_done = <span style='color:#b08000;'>1'b1</span>;
+
+<span style='color:#006e28;'>`endif</span>
+
+ <b>assign</b> tag_dirty = tagram_dirty_bit_set;
+
+ <span style='color:#898887;'>// WE to tag RAM</span>
+ <b>assign</b> tag_we = tagram_we_end_of_loadstore_loop |
+ tagram_dirty_bit_set | (state == <span \
style='color:#006e28;'>`OR1200_DCFSM_INV6</span>); +
+
+ <span style='color:#898887;'>// Valid bit</span>
+ <span style='color:#898887;'>// Set valid when end of line load, or marking dirty \
(is still valid)</span> + <b>assign</b> tag_valid = ( \
tagram_we_end_of_loadstore_loop & + (load | (store & \
cache_spr_block_writeback)) ) | + tagram_dirty_bit_set;
+
+
+
+ <span style='color:#898887;'>//</span>
+ <span style='color:#898887;'>// BIU read and write</span>
+ <span style='color:#898887;'>//</span>
+
+ <b>assign</b> biu_read = <span style='color:#898887;'>// Bus read request \
when:</span> + <span style='color:#898887;'>// 1) Have a miss and not dirty or \
a load with inhibit</span> + ((state == <span \
style='color:#006e28;'>`OR1200_DCFSM_CLOADSTORE</span>) & + \
(((hitmiss_eval & tagcomp_miss & !dirty & + !(store & \
writethrough)) | + (load & cache_inhibit_with_eval)) & dcqmem_cycstb_i)) |
+ <span style='color:#898887;'>// 2) In the loop and loading</span>
+ ((state == <span style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span>) & \
load); +
+
+ <b>assign</b> biu_write = <span style='color:#898887;'>// Bus write request \
when:</span> + <span style='color:#898887;'>// 1) Have a miss and dirty or \
store with inhibit</span> + ((state == <span \
style='color:#006e28;'>`OR1200_DCFSM_CLOADSTORE</span>) & + \
(((hitmiss_eval & tagcomp_miss & dirty) | + (store & writethrough)) | \
+ (store & cache_inhibit_with_eval)) & dcqmem_cycstb_i) |
+ <span style='color:#898887;'>// 2) In the loop and storing</span>
+ ((state == <span style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span>) & \
store); +
+ <span style='color:#898887;'>//</span>
+ <span style='color:#898887;'>// Select for data to actual cache RAM (from LSU or \
BIU)</span> + <span style='color:#898887;'>//</span>
+ <span style='color:#898887;'>// Data to DCRAM - from external bus when loading \
(from IU when store)</span> + <b>assign</b> dcram_di_sel = load;
+ <span style='color:#898887;'>// Data to external bus - always from IU except in \
case of bursting back</span> + <span style='color:#898887;'>// \
the line to memory. (1 selects DCRAM)</span> + <b>assign</b> biu_do_sel = (state == \
<span style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span>) & store; +
+ <span style='color:#898887;'>// 3-bit wire for calculating next word of burst \
write, depending on</span> + <span style='color:#898887;'>// line size of data \
cache.</span> + <b>assign</b> next_addr_word = addr_r[<span \
style='color:#006e28;'>`OR1200_DCLS</span>-<span \
style='color:#b08000;'>1</span>:<span style='color:#b08000;'>2</span>] + <span \
style='color:#b08000;'>1</span>; +
+ <span style='color:#898887;'>// Address to cache RAM (tag address also derived \
from this) </span> + <b>assign</b> dc_addr =
+ <span style='color:#898887;'>// First check if we've got a block flush or WB \
op</span> + ((dc_block_flush & !cache_spr_block_flush) |
+ (dc_block_writeback & !cache_spr_block_writeback)) ?
+ <span style='color:#b08000;'>spr_dat_i :</span>
+ (state==<span style='color:#006e28;'>`OR1200_DCFSM_FLUSH5</span>) ? addr_r:
+ <span style='color:#898887;'>// If no SPR action, then always put out address \
from LSU</span> + (state==<span style='color:#006e28;'>`OR1200_DCFSM_IDLE</span> \
| hitmiss_eval) ? lsu_addr : + <span style='color:#898887;'>// Next, if in \
writeback loop, when ACKed must immediately</span> + <span \
style='color:#898887;'>// output next word address (the RAM address takes a \
cycle</span> + <span style='color:#898887;'>// to increment, but it's needed \
immediately for burst)</span> + <span style='color:#898887;'>// otherwise, \
output our registered address.</span> + (state==<span \
style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span> & biudata_valid & store ) ? \
+ {addr_r[<span style='color:#b08000;'>31</span>:<span \
style='color:#006e28;'>`OR1200_DCLS</span>], next_addr_word, <span \
style='color:#b08000;'>2'b00</span>} : addr_r; +
+<span style='color:#006e28;'>`ifdef OR1200_DC_WRITETHROUGH</span>
+ <span style='color:#006e28;'>`ifdef</span> OR1200_DC_NOSTACKWRITETHROUGH
+ <b>assign</b> writethrough = !dc_no_writethrough;
+ <span style='color:#006e28;'>`else</span>
+ <b>assign</b> writethrough = <span style='color:#b08000;'>1</span>;
+ <span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`else</span>
+ <b>assign</b> writethrough = <span style='color:#b08000;'>0</span>;
+<span style='color:#006e28;'>`endif</span>
+
+ <span style='color:#898887;'>//</span>
+ <span style='color:#898887;'>// ACK generation for LSU</span>
+ <span style='color:#898887;'>//</span>
+
+ <span style='color:#898887;'>// ACK for when it's a cache hit</span>
+ <b>assign</b> first_hit_ack = load_hit_ack | store_hit_ack |
+ store_hit_writethrough_ack |
+ store_miss_writethrough_ack |
+ store_inhibit_ack | store_miss_ack ;
+
+ <span style='color:#898887;'>// ACK for when it's a cache miss - load only, is \
used in MUX for data back</span> + <span style='color:#898887;'>// \
LSU straight off external data bus. In</span> + <span style='color:#898887;'>// \
this was is also used for cache inhibit</span> + <span style='color:#898887;'>// \
loads.</span> + <span style='color:#898887;'>// first_hit_ack takes precedence over \
first_miss_ack</span> + <b>assign</b> first_miss_ack = ~first_hit_ack & \
(load_miss_ack | load_inhibit_ack); +
+ <span style='color:#898887;'>// ACK cache hit on load</span>
+ <b>assign</b> load_hit_ack = (state == <span \
style='color:#006e28;'>`OR1200_DCFSM_CLOADSTORE</span>) & + hitmiss_eval \
& !tagcomp_miss & !dcqmem_ci_i & load; +
+ <span style='color:#898887;'>// ACK cache hit on store, no writethrough</span>
+ <b>assign</b> store_hit_ack = (state == <span \
style='color:#006e28;'>`OR1200_DCFSM_CLOADSTORE</span>) & + hitmiss_eval \
& !tagcomp_miss & !dcqmem_ci_i & + store & !writethrough;
+
+ <span style='color:#898887;'>// ACK cache hit on store with writethrough</span>
+ <b>assign</b> store_hit_writethrough_ack = (state == <span \
style='color:#006e28;'>`OR1200_DCFSM_CLOADSTORE</span>) & + \
!cache_miss & !cache_inhibit & + store & writethrough & \
biudata_valid; +
+ <span style='color:#898887;'>// ACK cache miss on store with writethrough</span>
+ <b>assign</b> store_miss_writethrough_ack = (state == <span \
style='color:#006e28;'>`OR1200_DCFSM_CLOADSTORE</span>) & + cache_miss & \
!cache_inhibit & + store & writethrough & biudata_valid;
+
+ <span style='color:#898887;'>// ACK store when cacheinhibit</span>
+ <b>assign</b> store_inhibit_ack = (state == <span \
style='color:#006e28;'>`OR1200_DCFSM_CLOADSTORE</span>) & + store & \
cache_inhibit & biudata_valid; +
+
+ <span style='color:#898887;'>// Get the _early_ ack on first ACK back from \
wishbone during load only</span> + <span style='color:#898887;'>// Condition is \
that we're in the loop - that it's the first ack we get (can</span> + <span \
style='color:#898887;'>// tell from value of cnt), and we're loading a line to read \
from it (not</span> + <span style='color:#898887;'>// loading to write to it, in \
the case of a write without writethrough.)</span> + <b>assign</b> load_miss_ack = \
((state== <span style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span>) & load & \
+ (cnt==((<span style='color:#b08000;'>1</span> << <span \
style='color:#006e28;'>`OR1200_DCLS</span>) - <span style='color:#b08000;'>4</span>)) \
& biudata_valid & + !(dcqmem_we_i & !writethrough));
+
+ <b>assign</b> load_inhibit_ack = (state == <span \
style='color:#006e28;'>`OR1200_DCFSM_CLOADSTORE</span>) & + load & \
cache_inhibit & biudata_valid; +
+ <span style='color:#898887;'>// This will be case of write through disabled, and \
had to load a line.</span> + <b>assign</b> store_miss_ack = \
dcram_we_after_line_load; +
+ <b>assign</b> first_miss_err = biudata_error & dcqmem_cycstb_i;
+
+ <span style='color:#898887;'>// Signal burst when in the load/store loop. We will \
always try to burst.</span> + <b>assign</b> burst = (state == <span \
style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span>); +
+ <span style='color:#898887;'>//</span>
+ <span style='color:#898887;'>// Main DC FSM</span>
+ <span style='color:#898887;'>//</span>
+ <b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) <b>begin</b> + <b>if</b> \
(rst == <span style='color:#006e28;'>`OR1200_RST_VALUE</span>) <b>begin</b> + state \
<= <span style='color:#006e28;'>`OR1200_DCFSM_IDLE</span>; + addr_r <= <span \
style='color:#b08000;'>32'd0</span>; + hitmiss_eval <= <span \
style='color:#b08000;'>1'b0</span>; + store <= <span \
style='color:#b08000;'>1'b0</span>; + load <= <span \
style='color:#b08000;'>1'b0</span>; + cnt <= <span \
style='color:#006e28;'>`OR1200_DCLS</span><span style='color:#b08000;'>'d0</span>; + \
cache_miss <= <span style='color:#b08000;'>1'b0</span>; + \
cache_dirty_needs_writeback <= <span style='color:#b08000;'>1'b0</span>; + \
cache_inhibit <= <span style='color:#b08000;'>1'b0</span>; + did_early_load_ack \
<= <span style='color:#b08000;'>1'b0</span>; + cache_spr_block_flush <= <span \
style='color:#b08000;'>1'b0</span>; + cache_spr_block_writeback <= <span \
style='color:#b08000;'>1'b0</span>; + <b>end</b>
+ <b>else</b>
+ <b>case</b> (state) <span style='color:#898887;'>// synopsys parallel_case</span>
+
+ <span style='color:#006e28;'>`OR1200_DCFSM_IDLE</span> : <b>begin</b>
+ <b>if</b> (dc_en & (dc_block_flush | dc_block_writeback))
+ <b>begin</b>
+ cache_spr_block_flush <= dc_block_flush;
+ cache_spr_block_writeback <= dc_block_writeback;
+ hitmiss_eval <= <span style='color:#b08000;'>1'b1</span>;
+ state <= <span style='color:#006e28;'>`OR1200_DCFSM_FLUSH5</span>;
+ addr_r <= spr_dat_i;
+ <b>end</b>
+ <b>else</b> <b>if</b> (dc_en & dcqmem_cycstb_i)
+ <b>begin</b>
+ state <= <span style='color:#006e28;'>`OR1200_DCFSM_CLOADSTORE</span>;
+ hitmiss_eval <= <span style='color:#b08000;'>1'b1</span>;
+ store <= dcqmem_we_i;
+ load <= !dcqmem_we_i;
+ <b>end</b>
+
+
+ <b>end</b> <span style='color:#898887;'>// case: `OR1200_DCFSM_IDLE</span>
+
+ <span style='color:#006e28;'>`OR1200_DCFSM_CLOADSTORE</span>: <b>begin</b>
+ hitmiss_eval <= <span style='color:#b08000;'>1'b0</span>;
+ <b>if</b> (hitmiss_eval) <b>begin</b>
+ cache_inhibit <= dcqmem_ci_i; <span style='color:#898887;'>// \
Check for cache inhibit here</span> + cache_miss <= tagcomp_miss;
+ cache_dirty_needs_writeback <= dirty;
+ addr_r <= lsu_addr;
+ <b>end</b>
+
+ <span style='color:#898887;'>// Evaluate any cache line load/stores in first \
cycle:</span> + <span style='color:#898887;'>//</span>
+ <b>if</b> (hitmiss_eval & tagcomp_miss & !(store & writethrough) \
& + !dcqmem_ci_i)
+ <b>begin</b>
+ <span style='color:#898887;'>// Miss - first either:</span>
+ <span style='color:#898887;'>// 1) write back dirty line </span>
+ <b>if</b> (dirty) <b>begin</b>
+ <span style='color:#898887;'>// Address for writeback</span>
+ addr_r <= {tag, lsu_addr[<span \
style='color:#006e28;'>`OR1200_DCINDXH</span>:<span \
style='color:#b08000;'>2</span>],<span style='color:#b08000;'>2'd0</span>}; + \
load <= <span style='color:#b08000;'>1'b0</span>; + store <= <span \
style='color:#b08000;'>1'b1</span>; +<span style='color:#006e28;'>`ifdef \
OR1200_VERBOSE </span> + <span \
style='color:#0057ae;'>$display</span>(<span style='color:#bf0303;'>"%t: dcache \
miss and dirty"</span>, <span style='color:#0057ae;'>$time</span>); +<span \
style='color:#006e28;'>`endif</span> + <b>end</b>
+ <span style='color:#898887;'>// 2) load requested line</span>
+ <b>else</b> <b>begin</b>
+ addr_r <= lsu_addr;
+ load <= <span style='color:#b08000;'>1'b1</span>;
+ store <= <span style='color:#b08000;'>1'b0</span>;
+ <b>end</b> <span style='color:#898887;'>// else: !if(dirty)</span>
+ state <= <span style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span>;
+ <span style='color:#898887;'>// Set the counter for the burst accesses</span>
+ cnt <= ((<span style='color:#b08000;'>1</span> << <span \
style='color:#006e28;'>`OR1200_DCLS</span>) - <span style='color:#b08000;'>4</span>); \
+ <b>end</b> + <b>else</b> <b>if</b> (<span \
style='color:#898887;'>// Strobe goes low</span> + !dcqmem_cycstb_i |
+ <span style='color:#898887;'>// Cycle finishes</span>
+ (!hitmiss_eval & (biudata_valid | biudata_error)) |
+ <span style='color:#898887;'>// Cache hit in first cycle....</span>
+ (hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &
+ <span style='color:#898887;'>// .. and you're not doing a writethrough \
store..</span> + !(store & writethrough))) <b>begin</b>
+ state <= <span style='color:#006e28;'>`OR1200_DCFSM_IDLE</span>;
+ load <= <span style='color:#b08000;'>1'b0</span>;
+ store <= <span style='color:#b08000;'>1'b0</span>;
+ cache_inhibit <= <span style='color:#b08000;'>1'b0</span>;
+ cache_dirty_needs_writeback <= <span style='color:#b08000;'>1'b0</span>;
+ <b>end</b>
+ <b>end</b> <span style='color:#898887;'>// case: `OR1200_DCFSM_CLOADSTORE \
</span> +
+ <span style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span> : <b>begin</b> \
<span style='color:#898887;'>// loop/abort </span> + <b>if</b> \
(!dc_en| biudata_error) <b>begin</b> + state <= <span \
style='color:#006e28;'>`OR1200_DCFSM_IDLE</span>; + load <= <span \
style='color:#b08000;'>1'b0</span>; + store <= <span \
style='color:#b08000;'>1'b0</span>; + cnt <= <span \
style='color:#006e28;'>`OR1200_DCLS</span><span style='color:#b08000;'>'d0</span>; + \
<b>end</b> + <b>if</b> (biudata_valid & (|cnt)) <b>begin</b>
+ cnt <= cnt - <span style='color:#b08000;'>4</span>;
+ addr_r[<span style='color:#006e28;'>`OR1200_DCLS</span>-<span \
style='color:#b08000;'>1</span>:<span style='color:#b08000;'>2</span>] <= \
addr_r[<span style='color:#006e28;'>`OR1200_DCLS</span>-<span \
style='color:#b08000;'>1</span>:<span style='color:#b08000;'>2</span>] + <span \
style='color:#b08000;'>1</span>; + <b>end</b>
+ <b>else</b> <b>if</b> (biudata_valid & !(|cnt)) <b>begin</b>
+ state <= <span style='color:#006e28;'>`OR1200_DCFSM_LOOP3</span>;
+ addr_r <= lsu_addr;
+ load <= <span style='color:#b08000;'>1'b0</span>;
+ store <= <span style='color:#b08000;'>1'b0</span>;
+ <b>end</b>
+
+ <span style='color:#898887;'>// Track if we did an early ack during a \
load</span> + <b>if</b> (load_miss_ack)
+ did_early_load_ack <= <span style='color:#b08000;'>1'b1</span>;
+
+
+ <b>end</b> <span style='color:#898887;'>// case: \
`OR1200_DCFSM_LOOP2</span> +
+ <span style='color:#006e28;'>`OR1200_DCFSM_LOOP3</span>: <b>begin</b> <span \
style='color:#898887;'>// figure out next step</span> + <b>if</b> \
(cache_dirty_needs_writeback) <b>begin</b> + <span style='color:#898887;'>// Just \
did store of the dirty line so now load new one</span> + load <= <span \
style='color:#b08000;'>1'b1</span>; + <span style='color:#898887;'>// Set the \
counter for the burst accesses</span> + cnt <= ((<span \
style='color:#b08000;'>1</span> << <span \
style='color:#006e28;'>`OR1200_DCLS</span>) - <span style='color:#b08000;'>4</span>); \
+ <span style='color:#898887;'>// Address of line to be loaded</span> + addr_r \
<= lsu_addr; + cache_dirty_needs_writeback <= <span \
style='color:#b08000;'>1'b0</span>; + state <= <span \
style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span>; + <b>end</b> <span \
style='color:#898887;'>// if (cache_dirty_needs_writeback)</span> + <b>else</b> \
<b>if</b> (cache_spr_block_flush | cache_spr_block_writeback) <b>begin</b> + <span \
style='color:#898887;'>// Just wrote back the line to memory, we're finished.</span> \
+ cache_spr_block_flush <= <span style='color:#b08000;'>1'b0</span>; \
+ cache_spr_block_writeback <= <span style='color:#b08000;'>1'b0</span>; + state \
<= <span style='color:#006e28;'>`OR1200_DCFSM_WAITSPRCS7</span>; + <b>end</b>
+ <b>else</b> <b>begin</b>
+ <span style='color:#898887;'>// Just loaded a new line, finish up</span>
+ did_early_load_ack <= <span style='color:#b08000;'>1'b0</span>;
+ state <= <span style='color:#006e28;'>`OR1200_DCFSM_LOOP4</span>;
+ <b>end</b>
+ <b>end</b> <span style='color:#898887;'>// case: `OR1200_DCFSM_LOOP3</span>
+
+ <span style='color:#006e28;'>`OR1200_DCFSM_LOOP4</span>: <b>begin</b>
+ state <= <span style='color:#006e28;'>`OR1200_DCFSM_IDLE</span>;
+ <b>end</b>
+
+ <span style='color:#006e28;'>`OR1200_DCFSM_FLUSH5</span>: <b>begin</b>
+ hitmiss_eval <= <span style='color:#b08000;'>1'b0</span>;
+ <b>if</b> (hitmiss_eval & !tag_v)
+ <b>begin</b>
+ <span style='color:#898887;'>// Not even cached, just ignore</span>
+ cache_spr_block_flush <= <span style='color:#b08000;'>1'b0</span>;
+ cache_spr_block_writeback <= <span style='color:#b08000;'>1'b0</span>;
+ state <= <span style='color:#006e28;'>`OR1200_DCFSM_WAITSPRCS7</span>;
+ <b>end</b>
+ <b>else</b> <b>if</b> (hitmiss_eval & tag_v)
+ <b>begin</b>
+ <span style='color:#898887;'>// Tag is valid - what do we do?</span>
+ <b>if</b> ((cache_spr_block_flush | cache_spr_block_writeback) &
+ dirty) <b>begin</b>
+ <span style='color:#898887;'>// Need to writeback</span>
+ <span style='color:#898887;'>// Address for writeback (spr_dat_i has already \
changed so</span> + <span style='color:#898887;'>// use line number from \
addr_r)</span> + addr_r <= {tag, addr_r[<span \
style='color:#006e28;'>`OR1200_DCINDXH</span>:<span \
style='color:#b08000;'>2</span>],<span style='color:#b08000;'>2'd0</span>}; + \
load <= <span style='color:#b08000;'>1'b0</span>; + store <= <span \
style='color:#b08000;'>1'b1</span>; +<span style='color:#006e28;'>`ifdef \
OR1200_VERBOSE </span> + <span \
style='color:#0057ae;'>$display</span>(<span style='color:#bf0303;'>"%t: block \
flush: dirty block"</span>, <span style='color:#0057ae;'>$time</span>); +<span \
style='color:#006e28;'>`endif</span> + state <= <span \
style='color:#006e28;'>`OR1200_DCFSM_LOOP2</span>; + <span \
style='color:#898887;'>// Set the counter for the burst accesses</span> + cnt \
<= ((<span style='color:#b08000;'>1</span> << <span \
style='color:#006e28;'>`OR1200_DCLS</span>) - <span style='color:#b08000;'>4</span>); \
+ <b>end</b> + <b>else</b> <b>if</b> (cache_spr_block_flush & !dirty)
+ <b>begin</b>
+ <span style='color:#898887;'>// Line not dirty, just need to \
invalidate</span> + state <= <span \
style='color:#006e28;'>`OR1200_DCFSM_INV6</span>; + <b>end</b> <span \
style='color:#898887;'>// else: !if(dirty)</span> + <b>else</b> <b>if</b> \
(cache_spr_block_writeback & !dirty) + <b>begin</b>
+ <span style='color:#898887;'>// Nothing to do - line is valid but not \
dirty</span> + cache_spr_block_writeback <= <span \
style='color:#b08000;'>1'b0</span>; + state <= <span \
style='color:#006e28;'>`OR1200_DCFSM_WAITSPRCS7</span>; + <b>end</b>
+ <b>end</b> <span style='color:#898887;'>// if (hitmiss_eval & tag_v)</span>
+ <b>end</b>
+ <span style='color:#006e28;'>`OR1200_DCFSM_INV6</span>: <b>begin</b>
+ cache_spr_block_flush <= <span style='color:#b08000;'>1'b0</span>;
+ <span style='color:#898887;'>// Wait until SPR CS goes low before going back \
to idle</span> + <b>if</b> (!spr_cswe)
+ state <= <span style='color:#006e28;'>`OR1200_DCFSM_IDLE</span>;
+ <b>end</b>
+ <span style='color:#006e28;'>`OR1200_DCFSM_WAITSPRCS7</span>: <b>begin</b>
+ <span style='color:#898887;'>// Wait until SPR CS goes low before going back \
to idle</span> + <b>if</b> (!spr_cswe)
+ state <= <span style='color:#006e28;'>`OR1200_DCFSM_IDLE</span>;
+ <b>end</b>
+
+ <b>endcase</b> <span style='color:#898887;'>// case (state)</span>
+
+ <b>end</b> <span style='color:#898887;'>// always @ (posedge clk or \
`OR1200_RST_EVENT rst)</span> +
+
+<b>endmodule</b>
+</pre>
+</body>
+</html>
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "DTD/xhtml1-strict.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
+<meta name="Generator" content="Kate, the KDE Advanced Text Editor" />
+<title>or1200_du.v</title>
+</head>
+<body>
+<pre style='color:#1f1c1b;background-color:#ffffff;'>
+<span style='color:#898887;'>//////////////////////////////////////////////////////////////////////</span>
+<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// OR1200's Debug Unit \
////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// This file is part of the OpenRISC \
1200 project ////</span> +<span style='color:#898887;'>//// \
http://www.opencores.org/project,or1k ////</span> +<span \
style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// Description \
////</span> +<span style='color:#898887;'>//// Basic OR1200 debug unit. \
////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// To Do: \
////</span> +<span style='color:#898887;'>//// - make it smaller and faster \
////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// Author(s): \
////</span> +<span style='color:#898887;'>//// - Damjan Lampret, \
lampret@opencores.org ////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//////////////////////////////////////////////////////////////////////</span>
+<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// Copyright (C) 2000 Authors and \
OPENCORES.ORG ////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// This source file may be used and \
distributed without ////</span> +<span style='color:#898887;'>//// \
restriction provided that this copyright statement is not ////</span> +<span \
style='color:#898887;'>//// removed from the file and that any derivative work \
contains ////</span> +<span style='color:#898887;'>//// the original copyright \
notice and the associated disclaimer. ////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// This source file is free software; you \
can redistribute it ////</span> +<span style='color:#898887;'>//// and/or modify it \
under the terms of the GNU Lesser General ////</span> +<span \
style='color:#898887;'>//// Public License as published by the Free Software \
Foundation; ////</span> +<span style='color:#898887;'>//// either version 2.1 of the \
License, or (at your option) any ////</span> +<span style='color:#898887;'>//// \
later version. ////</span> +<span \
style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// This source is distributed in the hope \
that it will be ////</span> +<span style='color:#898887;'>//// useful, but \
WITHOUT ANY WARRANTY; without even the implied ////</span> +<span \
style='color:#898887;'>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \
////</span> +<span style='color:#898887;'>//// PURPOSE. See the GNU Lesser General \
Public License for more ////</span> +<span style='color:#898887;'>//// details. \
////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//// You should have received a copy of the \
GNU Lesser General ////</span> +<span style='color:#898887;'>//// Public License \
along with this source; if not, download it ////</span> +<span \
style='color:#898887;'>//// from http://www.opencores.org/lgpl.shtml \
////</span> +<span style='color:#898887;'>//// \
////</span> +<span style='color:#898887;'>//////////////////////////////////////////////////////////////////////</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// $Log: or1200_du.v,v $</span>
+<span style='color:#898887;'>// Revision 2.0 2010/06/30 11:00:00 ORSoC</span>
+<span style='color:#898887;'>// Minor update: </span>
+<span style='color:#898887;'>// Bugs fixed. </span>
+
+<span style='color:#898887;'>// synopsys translate_off</span>
+<span style='color:#006e28;'>`include </span><span \
style='color:#b08000;'>"timescale.v"</span> +<span \
style='color:#898887;'>// synopsys translate_on</span> +<span \
style='color:#006e28;'>`include </span><span \
style='color:#b08000;'>"or1200_defines.v"</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug unit</span>
+<span style='color:#898887;'>//</span>
+
+<b>module</b> or1200_du(
+ <span style='color:#898887;'>// RISC Internal Interface</span>
+ clk, rst,
+ dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
+ dcpu_dat_dc, icpu_cycstb_i,
+ ex_freeze, branch_op, ex_insn, id_pc,
+ spr_dat_npc, rf_dataw,
+ du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
+ du_read, du_write, du_except_stop, du_hwbkpt, du_flush_pipe,
+ spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
+
+ <span style='color:#898887;'>// External Debug Interface</span>
+ dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
+ dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
+);
+
+<span style='color:#0057ae;'>parameter</span> dw = <span \
style='color:#006e28;'>`OR1200_OPERAND_WIDTH</span>; +<span \
style='color:#0057ae;'>parameter</span> aw = <span \
style='color:#006e28;'>`OR1200_OPERAND_WIDTH</span>; +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// I/O</span>
+<span style='color:#898887;'>//</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// RISC Internal Interface</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#0057ae;'>input</span> clk; <span style='color:#898887;'>// \
Clock</span> +<span style='color:#0057ae;'>input</span> rst; <span \
style='color:#898887;'>// Reset</span> +<span \
style='color:#0057ae;'>input</span> dcpu_cycstb_i; <span style='color:#898887;'>// \
LSU status</span> +<span style='color:#0057ae;'>input</span> dcpu_we_i; <span \
style='color:#898887;'>// LSU status</span> +<span \
style='color:#0057ae;'>input</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dcpu_adr_i; <span style='color:#898887;'>// LSU \
addr</span> +<span style='color:#0057ae;'>input</span> [<span \
style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dcpu_dat_lsu; <span style='color:#898887;'>// LSU \
store data</span> +<span style='color:#0057ae;'>input</span> [<span \
style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dcpu_dat_dc; <span style='color:#898887;'>// LSU \
load data</span> +<span style='color:#0057ae;'>input</span> [<span \
style='color:#006e28;'>`OR1200_FETCHOP_WIDTH</span>-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] icpu_cycstb_i; <span style='color:#898887;'>// \
IFETCH unit status</span> +<span \
style='color:#0057ae;'>input</span> ex_freeze; <span style='color:#898887;'>// EX \
stage freeze</span> +<span style='color:#0057ae;'>input</span> [<span \
style='color:#006e28;'>`OR1200_BRANCHOP_WIDTH</span>-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] branch_op; <span style='color:#898887;'>// Branch \
op</span> +<span style='color:#0057ae;'>input</span> [dw-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] ex_insn; <span style='color:#898887;'>// EX \
insn</span> +<span style='color:#0057ae;'>input</span> [<span \
style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] id_pc; <span style='color:#898887;'>// insn fetch \
EA</span> +<span style='color:#0057ae;'>input</span> [<span \
style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] spr_dat_npc; <span style='color:#898887;'>// Next \
PC (for trace)</span> +<span style='color:#0057ae;'>input</span> [<span \
style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] rf_dataw; <span style='color:#898887;'>// ALU \
result (for trace)</span> +<span style='color:#0057ae;'>output</span> [<span \
style='color:#006e28;'>`OR1200_DU_DSR_WIDTH</span>-<span \
style='color:#b08000;'>1</span>:<span style='color:#b08000;'>0</span>] \
du_dsr; <span style='color:#898887;'>// DSR</span> +<span \
style='color:#0057ae;'>output</span> [<span style='color:#b08000;'>24</span>: <span \
style='color:#b08000;'>0</span>] du_dmr1; +<span \
style='color:#0057ae;'>output</span> du_stall; <span style='color:#898887;'>// \
Debug Unit Stall</span> +<span style='color:#0057ae;'>output</span> [aw-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] du_addr; <span style='color:#898887;'>// Debug Unit \
Address</span> +<span style='color:#0057ae;'>input</span> [dw-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] du_dat_i; <span style='color:#898887;'>// Debug \
Unit Data In</span> +<span style='color:#0057ae;'>output</span> [dw-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] du_dat_o; <span style='color:#898887;'>// Debug \
Unit Data Out</span> +<span style='color:#0057ae;'>output</span> du_read; <span \
style='color:#898887;'>// Debug Unit Read Enable</span> +<span \
style='color:#0057ae;'>output</span> du_write; <span style='color:#898887;'>// \
Debug Unit Write Enable</span> +<span style='color:#0057ae;'>input</span> [<span \
style='color:#b08000;'>13</span>:<span \
style='color:#b08000;'>0</span>] du_except_stop; <span style='color:#898887;'>// \
Exception masked by DSR</span> +<span \
style='color:#0057ae;'>output</span> du_hwbkpt; <span style='color:#898887;'>// \
Cause trap exception (HW Breakpoints)</span> +<span \
style='color:#0057ae;'>output</span> du_flush_pipe; <span \
style='color:#898887;'>// Cause pipeline flush and pc<-npc</span> +<span \
style='color:#0057ae;'>input</span> spr_cs; <span style='color:#898887;'>// SPR \
Chip Select</span> +<span style='color:#0057ae;'>input</span> spr_write; <span \
style='color:#898887;'>// SPR Read/Write</span> +<span \
style='color:#0057ae;'>input</span> [aw-<span style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] spr_addr; <span style='color:#898887;'>// SPR \
Address</span> +<span style='color:#0057ae;'>input</span> [dw-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] spr_dat_i; <span style='color:#898887;'>// SPR Data \
Input</span> +<span style='color:#0057ae;'>output</span> [dw-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] spr_dat_o; <span style='color:#898887;'>// SPR Data \
Output</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// External Debug Interface</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#0057ae;'>input</span> dbg_stall_i; <span \
style='color:#898887;'>// External Stall Input</span> +<span \
style='color:#0057ae;'>input</span> dbg_ewt_i; <span style='color:#898887;'>// \
External Watchpoint Trigger Input</span> +<span \
style='color:#0057ae;'>output</span> [<span style='color:#b08000;'>3</span>:<span \
style='color:#b08000;'>0</span>] dbg_lss_o; <span style='color:#898887;'>// External \
Load/Store Unit Status</span> +<span style='color:#0057ae;'>output</span> [<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] dbg_is_o; <span style='color:#898887;'>// External \
Insn Fetch Status</span> +<span style='color:#0057ae;'>output</span> [<span \
style='color:#b08000;'>10</span>:<span \
style='color:#b08000;'>0</span>] dbg_wp_o; <span style='color:#898887;'>// \
Watchpoints Outputs</span> +<span \
style='color:#0057ae;'>output</span> dbg_bp_o; <span style='color:#898887;'>// \
Breakpoint Output</span> +<span style='color:#0057ae;'>input</span> dbg_stb_i; \
<span style='color:#898887;'>// External Address/Data Strobe</span> +<span \
style='color:#0057ae;'>input</span> dbg_we_i; <span style='color:#898887;'>// \
External Write Enable</span> +<span style='color:#0057ae;'>input</span> [aw-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] dbg_adr_i; <span style='color:#898887;'>// External \
Address Input</span> +<span style='color:#0057ae;'>input</span> [dw-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] dbg_dat_i; <span style='color:#898887;'>// External \
Data Input</span> +<span style='color:#0057ae;'>output</span> [dw-<span \
style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] dbg_dat_o; <span style='color:#898887;'>// External \
Data Output</span> +<span style='color:#0057ae;'>output</span> dbg_ack_o; <span \
style='color:#898887;'>// External Data Acknowledge (not WB compatible)</span> +<span \
style='color:#0057ae;'>reg</span> [dw-<span style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] dbg_dat_o; <span style='color:#898887;'>// External \
Data Output</span> +<span style='color:#0057ae;'>reg</span> dbg_ack_o; <span \
style='color:#898887;'>// External Data Acknowledge (not WB compatible)</span> +
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Some connections go directly from the CPU through DU \
to Debug I/F</span> +<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_STATUS_UNIMPLEMENTED</span>
+<b>assign</b> dbg_lss_o = <span style='color:#b08000;'>4'b0000</span>;
+
+<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>1</span>:<span \
style='color:#b08000;'>0</span>] dbg_is_o; +<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Show insn activity (temp, must be removed)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dbg_is_o <= <span \
style='color:#b08000;'>2'b00</span>; + <b>else</b> <b>if</b> (!ex_freeze & \
~((ex_insn[<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>26</span>] == <span \
style='color:#006e28;'>`OR1200_OR32_NOP</span>) & ex_insn[<span \
style='color:#b08000;'>16</span>])) + dbg_is_o <= ~dbg_is_o;
+<span style='color:#006e28;'>`ifdef UNUSED</span>
+<b>assign</b> dbg_is_o = <span style='color:#b08000;'>2'b00</span>;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`else</span>
+<b>assign</b> dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, <span \
style='color:#b08000;'>3'b000</span>} : <span style='color:#b08000;'>4'b0000</span>; \
+<b>assign</b> dbg_is_o = {<span style='color:#b08000;'>1'b0</span>, icpu_cycstb_i}; \
+<span style='color:#006e28;'>`endif</span> +<b>assign</b> dbg_wp_o = <span \
style='color:#b08000;'>11'b000_0000_0000</span>; +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Some connections go directly from Debug I/F through \
DU to the CPU</span> +<span style='color:#898887;'>//</span>
+<b>assign</b> du_stall = dbg_stall_i;
+<b>assign</b> du_addr = dbg_adr_i;
+<b>assign</b> du_dat_o = dbg_dat_i;
+<b>assign</b> du_read = dbg_stb_i && !dbg_we_i;
+<b>assign</b> du_write = dbg_stb_i && dbg_we_i;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// After a sw breakpoint, the replaced instruction need \
to be executed.</span> +<span style='color:#898887;'>// We flush the entire pipeline \
and set the pc to the current address</span> +<span style='color:#898887;'>// to \
execute the restored address.</span> +<span style='color:#898887;'>//</span>
+
+<span style='color:#0057ae;'>reg</span> du_flush_pipe_r;
+<span style='color:#0057ae;'>reg</span> dbg_stall_i_r;
+
+<b>assign</b> du_flush_pipe = du_flush_pipe_r;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Register du_flush_pipe</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) <b>begin</b> + <b>if</b> (rst == \
<span style='color:#006e28;'>`OR1200_RST_VALUE</span>) <b>begin</b> \
+ du_flush_pipe_r <= <span style='color:#b08000;'>1'b0</span>; + <b>end</b>
+ <b>else</b> <b>begin</b>
+ du_flush_pipe_r <= (dbg_stall_i_r && !dbg_stall_i && \
|du_except_stop); + <b>end</b>
+<b>end</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Detect dbg_stall falling edge</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) <b>begin</b> + <b>if</b> (rst == \
<span style='color:#006e28;'>`OR1200_RST_VALUE</span>) <b>begin</b> + dbg_stall_i_r \
<= <span style='color:#b08000;'>1'b0</span>; + <b>end</b>
+ <b>else</b> <b>begin</b>
+ dbg_stall_i_r <= dbg_stall_i;
+ <b>end</b>
+<b>end</b>
+
+<span style='color:#0057ae;'>reg</span> dbg_ack;
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Generate acknowledge -- just delay stb signal</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) <b>begin</b> + <b>if</b> (rst == \
<span style='color:#006e28;'>`OR1200_RST_VALUE</span>) <b>begin</b> + dbg_ack \
<= <span style='color:#b08000;'>1'b0</span>; + dbg_ack_o <= <span \
style='color:#b08000;'>1'b0</span>; + <b>end</b>
+ <b>else</b> <b>begin</b>
+ dbg_ack <= dbg_stb_i; <span style='color:#898887;'>// valid when du_dat_i \
</span> + dbg_ack_o <= dbg_ack & dbg_stb_i; <span style='color:#898887;'>// \
valid when dbg_dat_o </span> + <b>end</b>
+<b>end</b>
+
+<span style='color:#898887;'>// </span>
+<span style='color:#898887;'>// Register data output</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(<b>posedge</b> clk)
+ dbg_dat_o <= du_dat_i;
+
+<span style='color:#006e28;'>`ifdef OR1200_DU_IMPLEMENTED</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Mode Register 1</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DMR1</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>24</span>:<span \
style='color:#b08000;'>0</span>] dmr1; <span style='color:#898887;'>// DMR1 \
implemented</span> +<span style='color:#006e28;'>`else</span>
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>24</span>:<span \
style='color:#b08000;'>0</span>] dmr1; <span style='color:#898887;'>// DMR1 not \
implemented</span> +<span style='color:#006e28;'>`endif</span>
+<b>assign</b> du_dmr1 = dmr1;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Mode Register 2</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DMR2</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>23</span>:<span \
style='color:#b08000;'>0</span>] dmr2; <span style='color:#898887;'>// DMR2 \
implemented</span> +<span style='color:#006e28;'>`else</span>
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>23</span>:<span \
style='color:#b08000;'>0</span>] dmr2; <span style='color:#898887;'>// DMR2 not \
implemented</span> +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Stop Register</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DSR</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#006e28;'>`OR1200_DU_DSR_WIDTH</span>-<span \
style='color:#b08000;'>1</span>:<span style='color:#b08000;'>0</span>] dsr; <span \
style='color:#898887;'>// DSR implemented</span> +<span \
style='color:#006e28;'>`else</span> +<span style='color:#0057ae;'>wire</span> [<span \
style='color:#006e28;'>`OR1200_DU_DSR_WIDTH</span>-<span \
style='color:#b08000;'>1</span>:<span style='color:#b08000;'>0</span>] dsr; <span \
style='color:#898887;'>// DSR not implemented</span> +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Reason Register</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DRR</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>13</span>:<span style='color:#b08000;'>0</span>] drr; <span \
style='color:#898887;'>// DRR implemented</span> +<span \
style='color:#006e28;'>`else</span> +<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>13</span>:<span style='color:#b08000;'>0</span>] drr; <span \
style='color:#898887;'>// DRR not implemented</span> +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Value Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR0</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] dvr0; \
+<span style='color:#006e28;'>`else</span> +<span \
style='color:#0057ae;'>wire</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dvr0; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Value Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR1</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] dvr1; \
+<span style='color:#006e28;'>`else</span> +<span \
style='color:#0057ae;'>wire</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dvr1; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Value Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR2</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] dvr2; \
+<span style='color:#006e28;'>`else</span> +<span \
style='color:#0057ae;'>wire</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dvr2; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Value Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR3</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] dvr3; \
+<span style='color:#006e28;'>`else</span> +<span \
style='color:#0057ae;'>wire</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dvr3; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Value Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR4</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] dvr4; \
+<span style='color:#006e28;'>`else</span> +<span \
style='color:#0057ae;'>wire</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dvr4; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Value Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR5</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] dvr5; \
+<span style='color:#006e28;'>`else</span> +<span \
style='color:#0057ae;'>wire</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dvr5; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Value Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR6</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] dvr6; \
+<span style='color:#006e28;'>`else</span> +<span \
style='color:#0057ae;'>wire</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dvr6; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Value Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR7</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] dvr7; \
+<span style='color:#006e28;'>`else</span> +<span \
style='color:#0057ae;'>wire</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dvr7; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Control Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR0</span>
+<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>] dcr0; +<span style='color:#006e28;'>`else</span>
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>7</span>:<span style='color:#b08000;'>0</span>] dcr0; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Control Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR1</span>
+<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>] dcr1; +<span style='color:#006e28;'>`else</span>
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>7</span>:<span style='color:#b08000;'>0</span>] dcr1; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Control Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR2</span>
+<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>] dcr2; +<span style='color:#006e28;'>`else</span>
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>7</span>:<span style='color:#b08000;'>0</span>] dcr2; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Control Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR3</span>
+<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>] dcr3; +<span style='color:#006e28;'>`else</span>
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>7</span>:<span style='color:#b08000;'>0</span>] dcr3; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Control Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR4</span>
+<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>] dcr4; +<span style='color:#006e28;'>`else</span>
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>7</span>:<span style='color:#b08000;'>0</span>] dcr4; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Control Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR5</span>
+<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>] dcr5; +<span style='color:#006e28;'>`else</span>
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>7</span>:<span style='color:#b08000;'>0</span>] dcr5; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Control Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR6</span>
+<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>] dcr6; +<span style='color:#006e28;'>`else</span>
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>7</span>:<span style='color:#b08000;'>0</span>] dcr6; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Control Register N</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR7</span>
+<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>] dcr7; +<span style='color:#006e28;'>`else</span>
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>7</span>:<span style='color:#b08000;'>0</span>] dcr7; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Watchpoint Counter Register 0</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DWCR0</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] dwcr0; \
+<span style='color:#006e28;'>`else</span> +<span \
style='color:#0057ae;'>wire</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dwcr0; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Debug Watchpoint Counter Register 1</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DWCR1</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] dwcr1; \
+<span style='color:#006e28;'>`else</span> +<span \
style='color:#0057ae;'>wire</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] dwcr1; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Internal wires</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#0057ae;'>wire</span> dmr1_sel; <span \
style='color:#898887;'>// DMR1 select</span> +<span \
style='color:#0057ae;'>wire</span> dmr2_sel; <span style='color:#898887;'>// DMR2 \
select</span> +<span style='color:#0057ae;'>wire</span> dsr_sel; <span \
style='color:#898887;'>// DSR select</span> +<span \
style='color:#0057ae;'>wire</span> drr_sel; <span style='color:#898887;'>// DRR \
select</span> +<span style='color:#0057ae;'>wire</span> dvr0_sel,
+ dvr1_sel,
+ dvr2_sel,
+ dvr3_sel,
+ dvr4_sel,
+ dvr5_sel,
+ dvr6_sel,
+ dvr7_sel; <span style='color:#898887;'>// DVR selects</span>
+<span style='color:#0057ae;'>wire</span> dcr0_sel,
+ dcr1_sel,
+ dcr2_sel,
+ dcr3_sel,
+ dcr4_sel,
+ dcr5_sel,
+ dcr6_sel,
+ dcr7_sel; <span style='color:#898887;'>// DCR selects</span>
+<span style='color:#0057ae;'>wire</span> dwcr0_sel,
+ dwcr1_sel; <span style='color:#898887;'>// DWCR selects</span>
+<span style='color:#0057ae;'>reg</span> dbg_bp_r;
+<span style='color:#0057ae;'>reg</span> ex_freeze_q;
+<span style='color:#006e28;'>`ifdef OR1200_DU_HWBKPTS</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] match_cond0_ct; +<span \
style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] match_cond1_ct; +<span \
style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] match_cond2_ct; +<span \
style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] match_cond3_ct; +<span \
style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] match_cond4_ct; +<span \
style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] match_cond5_ct; +<span \
style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] match_cond6_ct; +<span \
style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] match_cond7_ct; +<span \
style='color:#0057ae;'>reg</span> match_cond0_stb; +<span \
style='color:#0057ae;'>reg</span> match_cond1_stb; +<span \
style='color:#0057ae;'>reg</span> match_cond2_stb; +<span \
style='color:#0057ae;'>reg</span> match_cond3_stb; +<span \
style='color:#0057ae;'>reg</span> match_cond4_stb; +<span \
style='color:#0057ae;'>reg</span> match_cond5_stb; +<span \
style='color:#0057ae;'>reg</span> match_cond6_stb; +<span \
style='color:#0057ae;'>reg</span> match_cond7_stb; +<span \
style='color:#0057ae;'>reg</span> match0; +<span \
style='color:#0057ae;'>reg</span> match1; +<span \
style='color:#0057ae;'>reg</span> match2; +<span \
style='color:#0057ae;'>reg</span> match3; +<span \
style='color:#0057ae;'>reg</span> match4; +<span \
style='color:#0057ae;'>reg</span> match5; +<span \
style='color:#0057ae;'>reg</span> match6; +<span \
style='color:#0057ae;'>reg</span> match7; +<span \
style='color:#0057ae;'>reg</span> wpcntr0_match; +<span \
style='color:#0057ae;'>reg</span> wpcntr1_match; +<span \
style='color:#0057ae;'>reg</span> incr_wpcntr0; +<span \
style='color:#0057ae;'>reg</span> incr_wpcntr1; +<span \
style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>10</span>:<span \
style='color:#b08000;'>0</span>] wp; +<span style='color:#006e28;'>`endif</span>
+<span style='color:#0057ae;'>wire</span> du_hwbkpt;
+<span style='color:#0057ae;'>reg</span> du_hwbkpt_hold;
+<span style='color:#006e28;'>`ifdef OR1200_DU_READREGS</span>
+<span style='color:#0057ae;'>reg</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] spr_dat_o; \
+<span style='color:#006e28;'>`endif</span> +<span \
style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>13</span>:<span \
style='color:#b08000;'>0</span>] except_stop; <span style='color:#898887;'>// \
Exceptions that stop because of DSR</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_TB_IMPLEMENTED</span> +<span style='color:#0057ae;'>wire</span> tb_enw;
+<span style='color:#0057ae;'>reg</span> [<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>] tb_wadr; +<span style='color:#0057ae;'>reg</span> \
[<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>0</span>] tb_timstmp; +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] tbia_dat_o; \
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] tbim_dat_o; \
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] tbar_dat_o; \
+<span style='color:#0057ae;'>wire</span> [<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>] tbts_dat_o; \
+ +<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// DU registers address decoder</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DMR1</span>
+<b>assign</b> dmr1_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DMR1</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DMR2</span> +<b>assign</b> dmr2_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DMR2</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DSR</span> +<b>assign</b> dsr_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DSR</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DRR</span> +<b>assign</b> drr_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DRR</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DVR0</span> +<b>assign</b> dvr0_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DVR0</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DVR1</span> +<b>assign</b> dvr1_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DVR1</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DVR2</span> +<b>assign</b> dvr2_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DVR2</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DVR3</span> +<b>assign</b> dvr3_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DVR3</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DVR4</span> +<b>assign</b> dvr4_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DVR4</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DVR5</span> +<b>assign</b> dvr5_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DVR5</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DVR6</span> +<b>assign</b> dvr6_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DVR6</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DVR7</span> +<b>assign</b> dvr7_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DVR7</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DCR0</span> +<b>assign</b> dcr0_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DCR0</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DCR1</span> +<b>assign</b> dcr1_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DCR1</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DCR2</span> +<b>assign</b> dcr2_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DCR2</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DCR3</span> +<b>assign</b> dcr3_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DCR3</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DCR4</span> +<b>assign</b> dcr4_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DCR4</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DCR5</span> +<b>assign</b> dcr5_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DCR5</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DCR6</span> +<b>assign</b> dcr6_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DCR6</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DCR7</span> +<b>assign</b> dcr7_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DCR7</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DWCR0</span> +<b>assign</b> dwcr0_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DWCR0</span>)); +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DWCR1</span> +<b>assign</b> dwcr1_sel = (spr_cs && (spr_addr[<span \
style='color:#006e28;'>`OR1200_DUOFS_BITS</span>] == <span \
style='color:#006e28;'>`OR1200_DU_DWCR1</span>)); +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>// Track previous ex_freeze to detect when signals are \
updated</span> +<b>always</b> @(<b>posedge</b> clk)
+ ex_freeze_q <= ex_freeze;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Decode started exception</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// du_except_stop comes from or1200_except</span>
+<span style='color:#898887;'>// </span>
+<b>always</b> @(du_except_stop <span style='color:#0057ae;'>or</span> ex_freeze_q) \
<b>begin</b> + except_stop = <span \
style='color:#b08000;'>14'b00_0000_0000_0000</span>; + <b>casez</b> (du_except_stop)
+ <span style='color:#b08000;'>14'b1</span>?_????_????_????:
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_TTE</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <span \
style='color:#b08000;'>14'b01_</span>????_????_????: <b>begin</b> \
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_IE</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <b>end</b>
+ <span style='color:#b08000;'>14'b00_1</span>???_????_????: <b>begin</b>
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_IME</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <b>end</b>
+ <span style='color:#b08000;'>14'b00_01</span>??_????_????:
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_IPFE</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <span \
style='color:#b08000;'>14'b00_001</span>?_????_????: <b>begin</b> \
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_BUSEE</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <b>end</b>
+ <span style='color:#b08000;'>14'b00_0001_</span>????_????:
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_IIE</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <span \
style='color:#b08000;'>14'b00_0000_1</span>???_????: <b>begin</b> \
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_AE</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <b>end</b>
+ <span style='color:#b08000;'>14'b00_0000_01</span>??_????: <b>begin</b>
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_DME</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <b>end</b>
+ <span style='color:#b08000;'>14'b00_0000_001</span>?_????:
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_DPFE</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <span \
style='color:#b08000;'>14'b00_0000_0001_</span>????: + except_stop[<span \
style='color:#006e28;'>`OR1200_DU_DRR_BUSEE</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <span \
style='color:#b08000;'>14'b00_0000_0000_1</span>???: <b>begin</b> \
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_RE</span>] = <span \
style='color:#b08000;'>1'b1</span>; + <b>end</b>
+ <span style='color:#b08000;'>14'b00_0000_0000_01</span>??: <b>begin</b>
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_TE</span>] = <span \
style='color:#b08000;'>1'b1</span> & ~ex_freeze_q; + <b>end</b>
+ <span style='color:#b08000;'>14'b00_0000_0000_001</span>?: <b>begin</b>
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_FPE</span>] = \
<span style='color:#b08000;'>1'b1</span>; + <b>end</b>
+ <span style='color:#b08000;'>14'b00_0000_0000_0001</span>:
+ except_stop[<span style='color:#006e28;'>`OR1200_DU_DRR_SCE</span>] = <span \
style='color:#b08000;'>1'b1</span> & ~ex_freeze_q; + <b>default</b>:
+ except_stop = <span style='color:#b08000;'>14'b00_0000_0000_0000</span>;
+ <b>endcase</b> <span style='color:#898887;'>// casez (du_except_stop)</span>
+<b>end</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// dbg_bp_o is registered</span>
+<span style='color:#898887;'>//</span>
+<b>assign</b> dbg_bp_o = dbg_bp_r;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Breakpoint activation register</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dbg_bp_r <= <span \
style='color:#b08000;'>1'b0</span>; + <b>else</b> <b>if</b> (!ex_freeze)
+ dbg_bp_r <= |except_stop
+<span style='color:#006e28;'>`ifdef OR1200_DU_DMR1_ST</span>
+ | ~((ex_insn[<span style='color:#b08000;'>31</span>:<span \
style='color:#b08000;'>26</span>] == <span \
style='color:#006e28;'>`OR1200_OR32_NOP</span>) & ex_insn[<span \
style='color:#b08000;'>16</span>]) & dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_ST</span>] +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`ifdef \
OR1200_DU_DMR1_BT</span> + | (branch_op != <span \
style='color:#006e28;'>`OR1200_BRANCHOP_NOP</span>) & (branch_op != <span \
style='color:#006e28;'>`OR1200_BRANCHOP_RFE</span>) & dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_BT</span>] +<span \
style='color:#006e28;'>`endif</span> + ;
+ <b>else</b>
+ dbg_bp_r <= |except_stop;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DMR1</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DMR1</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dmr1 <= <span \
style='color:#b08000;'>25'h000_0000</span>; + <b>else</b> <b>if</b> (dmr1_sel \
&& spr_write) +<span style='color:#006e28;'>`ifdef OR1200_DU_HWBKPTS</span>
+ dmr1 <= spr_dat_i[<span style='color:#b08000;'>24</span>:<span \
style='color:#b08000;'>0</span>]; +<span style='color:#006e28;'>`else</span>
+ dmr1 <= {<span style='color:#b08000;'>1'b0</span>, spr_dat_i[<span \
style='color:#b08000;'>23</span>:<span style='color:#b08000;'>22</span>], <span \
style='color:#b08000;'>22'h00_0000</span>}; +<span \
style='color:#006e28;'>`endif</span> +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dmr1 = <span style='color:#b08000;'>25'h000_0000</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DMR2</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DMR2</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dmr2 <= <span \
style='color:#b08000;'>24'h00_0000</span>; + <b>else</b> <b>if</b> (dmr2_sel \
&& spr_write) + dmr2 <= spr_dat_i[<span \
style='color:#b08000;'>23</span>:<span style='color:#b08000;'>0</span>]; +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> dmr2 = <span \
style='color:#b08000;'>24'h00_0000</span>; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DSR</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DSR</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dsr <= {<span \
style='color:#006e28;'>`OR1200_DU_DSR_WIDTH</span>{<span \
style='color:#b08000;'>1'b0</span>}}; + <b>else</b> <b>if</b> (dsr_sel && \
spr_write) + dsr <= spr_dat_i[<span \
style='color:#006e28;'>`OR1200_DU_DSR_WIDTH</span>-<span \
style='color:#b08000;'>1</span>:<span style='color:#b08000;'>0</span>]; +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> dsr = {<span \
style='color:#006e28;'>`OR1200_DU_DSR_WIDTH</span>{<span \
style='color:#b08000;'>1'b0</span>}}; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DRR</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DRR</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + drr <= <span \
style='color:#b08000;'>14'b0</span>; + <b>else</b> <b>if</b> (drr_sel && \
spr_write) + drr <= spr_dat_i[<span style='color:#b08000;'>13</span>:<span \
style='color:#b08000;'>0</span>]; + <b>else</b>
+ drr <= drr | except_stop;
+<span style='color:#006e28;'>`else</span>
+<b>assign</b> drr = <span style='color:#b08000;'>14'b0</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DVR0</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR0</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dvr0 <= <span \
style='color:#b08000;'>32'h0000_0000</span>; + <b>else</b> <b>if</b> (dvr0_sel \
&& spr_write) + dvr0 <= spr_dat_i[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>]; +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> dvr0 = <span \
style='color:#b08000;'>32'h0000_0000</span>; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DVR1</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR1</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dvr1 <= <span \
style='color:#b08000;'>32'h0000_0000</span>; + <b>else</b> <b>if</b> (dvr1_sel \
&& spr_write) + dvr1 <= spr_dat_i[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>]; +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> dvr1 = <span \
style='color:#b08000;'>32'h0000_0000</span>; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DVR2</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR2</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dvr2 <= <span \
style='color:#b08000;'>32'h0000_0000</span>; + <b>else</b> <b>if</b> (dvr2_sel \
&& spr_write) + dvr2 <= spr_dat_i[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>]; +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> dvr2 = <span \
style='color:#b08000;'>32'h0000_0000</span>; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DVR3</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR3</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dvr3 <= <span \
style='color:#b08000;'>32'h0000_0000</span>; + <b>else</b> <b>if</b> (dvr3_sel \
&& spr_write) + dvr3 <= spr_dat_i[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>]; +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> dvr3 = <span \
style='color:#b08000;'>32'h0000_0000</span>; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DVR4</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR4</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dvr4 <= <span \
style='color:#b08000;'>32'h0000_0000</span>; + <b>else</b> <b>if</b> (dvr4_sel \
&& spr_write) + dvr4 <= spr_dat_i[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>]; +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> dvr4 = <span \
style='color:#b08000;'>32'h0000_0000</span>; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DVR5</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR5</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dvr5 <= <span \
style='color:#b08000;'>32'h0000_0000</span>; + <b>else</b> <b>if</b> (dvr5_sel \
&& spr_write) + dvr5 <= spr_dat_i[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>]; +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> dvr5 = <span \
style='color:#b08000;'>32'h0000_0000</span>; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DVR6</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR6</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dvr6 <= <span \
style='color:#b08000;'>32'h0000_0000</span>; + <b>else</b> <b>if</b> (dvr6_sel \
&& spr_write) + dvr6 <= spr_dat_i[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>]; +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> dvr6 = <span \
style='color:#b08000;'>32'h0000_0000</span>; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DVR7</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR7</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dvr7 <= <span \
style='color:#b08000;'>32'h0000_0000</span>; + <b>else</b> <b>if</b> (dvr7_sel \
&& spr_write) + dvr7 <= spr_dat_i[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>]; +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> dvr7 = <span \
style='color:#b08000;'>32'h0000_0000</span>; +<span \
style='color:#006e28;'>`endif</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DCR0</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR0</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dcr0 <= <span \
style='color:#b08000;'>8'h00</span>; + <b>else</b> <b>if</b> (dcr0_sel && \
spr_write) + dcr0 <= spr_dat_i[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]; +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dcr0 = <span style='color:#b08000;'>8'h00</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DCR1</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR1</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dcr1 <= <span \
style='color:#b08000;'>8'h00</span>; + <b>else</b> <b>if</b> (dcr1_sel && \
spr_write) + dcr1 <= spr_dat_i[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]; +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dcr1 = <span style='color:#b08000;'>8'h00</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DCR2</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR2</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dcr2 <= <span \
style='color:#b08000;'>8'h00</span>; + <b>else</b> <b>if</b> (dcr2_sel && \
spr_write) + dcr2 <= spr_dat_i[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]; +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dcr2 = <span style='color:#b08000;'>8'h00</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DCR3</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR3</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dcr3 <= <span \
style='color:#b08000;'>8'h00</span>; + <b>else</b> <b>if</b> (dcr3_sel && \
spr_write) + dcr3 <= spr_dat_i[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]; +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dcr3 = <span style='color:#b08000;'>8'h00</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DCR4</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR4</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dcr4 <= <span \
style='color:#b08000;'>8'h00</span>; + <b>else</b> <b>if</b> (dcr4_sel && \
spr_write) + dcr4 <= spr_dat_i[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]; +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dcr4 = <span style='color:#b08000;'>8'h00</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DCR5</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR5</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dcr5 <= <span \
style='color:#b08000;'>8'h00</span>; + <b>else</b> <b>if</b> (dcr5_sel && \
spr_write) + dcr5 <= spr_dat_i[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]; +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dcr5 = <span style='color:#b08000;'>8'h00</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DCR6</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR6</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dcr6 <= <span \
style='color:#b08000;'>8'h00</span>; + <b>else</b> <b>if</b> (dcr6_sel && \
spr_write) + dcr6 <= spr_dat_i[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]; +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dcr6 = <span style='color:#b08000;'>8'h00</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DCR7</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR7</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dcr7 <= <span \
style='color:#b08000;'>8'h00</span>; + <b>else</b> <b>if</b> (dcr7_sel && \
spr_write) + dcr7 <= spr_dat_i[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]; +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dcr7 = <span style='color:#b08000;'>8'h00</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DWCR0</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DWCR0</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dwcr0 <= <span \
style='color:#b08000;'>32'h0000_0000</span>; + <b>else</b> <b>if</b> (dwcr0_sel \
&& spr_write) + dwcr0 <= spr_dat_i[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>]; \
+ <b>else</b> <b>if</b> (incr_wpcntr0) + dwcr0[<span \
style='color:#006e28;'>`OR1200_DU_DWCR_COUNT</span>] <= dwcr0[<span \
style='color:#006e28;'>`OR1200_DU_DWCR_COUNT</span>] + <span \
style='color:#b08000;'>16'h0001</span>; +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dwcr0 = <span style='color:#b08000;'>32'h0000_0000</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Write to DWCR1</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DWCR1</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + dwcr1 <= <span \
style='color:#b08000;'>32'h0000_0000</span>; + <b>else</b> <b>if</b> (dwcr1_sel \
&& spr_write) + dwcr1 <= spr_dat_i[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>0</span>]; \
+ <b>else</b> <b>if</b> (incr_wpcntr1) + dwcr1[<span \
style='color:#006e28;'>`OR1200_DU_DWCR_COUNT</span>] <= dwcr1[<span \
style='color:#006e28;'>`OR1200_DU_DWCR_COUNT</span>] + <span \
style='color:#b08000;'>16'h0001</span>; +<span style='color:#006e28;'>`else</span>
+<b>assign</b> dwcr1 = <span style='color:#b08000;'>32'h0000_0000</span>;
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Read DU registers</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_READREGS</span>
+<b>always</b> @(spr_addr <span style='color:#0057ae;'>or</span> dsr <span \
style='color:#0057ae;'>or</span> drr <span style='color:#0057ae;'>or</span> dmr1 \
<span style='color:#0057ae;'>or</span> dmr2 + <span style='color:#0057ae;'>or</span> \
dvr0 <span style='color:#0057ae;'>or</span> dvr1 <span \
style='color:#0057ae;'>or</span> dvr2 <span style='color:#0057ae;'>or</span> dvr3 \
<span style='color:#0057ae;'>or</span> dvr4 + <span style='color:#0057ae;'>or</span> \
dvr5 <span style='color:#0057ae;'>or</span> dvr6 <span \
style='color:#0057ae;'>or</span> dvr7 + <span style='color:#0057ae;'>or</span> dcr0 \
<span style='color:#0057ae;'>or</span> dcr1 <span style='color:#0057ae;'>or</span> \
dcr2 <span style='color:#0057ae;'>or</span> dcr3 <span \
style='color:#0057ae;'>or</span> dcr4 + <span style='color:#0057ae;'>or</span> dcr5 \
<span style='color:#0057ae;'>or</span> dcr6 <span style='color:#0057ae;'>or</span> \
dcr7 + <span style='color:#0057ae;'>or</span> dwcr0 <span \
style='color:#0057ae;'>or</span> dwcr1 +<span style='color:#006e28;'>`ifdef \
OR1200_DU_TB_IMPLEMENTED</span> + <span style='color:#0057ae;'>or</span> tb_wadr \
<span style='color:#0057ae;'>or</span> tbia_dat_o <span \
style='color:#0057ae;'>or</span> tbim_dat_o + <span style='color:#0057ae;'>or</span> \
tbar_dat_o <span style='color:#0057ae;'>or</span> tbts_dat_o +<span \
style='color:#006e28;'>`endif</span> + )
+ <b>casez</b> (spr_addr[<span style='color:#006e28;'>`OR1200_DUOFS_BITS</span>]) \
<span style='color:#898887;'>// synopsys parallel_case</span> +<span \
style='color:#006e28;'>`ifdef OR1200_DU_DVR0</span> + <span \
style='color:#006e28;'>`OR1200_DU_DVR0</span>: + spr_dat_o = dvr0;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR1</span>
+ <span style='color:#006e28;'>`OR1200_DU_DVR1</span>:
+ spr_dat_o = dvr1;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR2</span>
+ <span style='color:#006e28;'>`OR1200_DU_DVR2</span>:
+ spr_dat_o = dvr2;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR3</span>
+ <span style='color:#006e28;'>`OR1200_DU_DVR3</span>:
+ spr_dat_o = dvr3;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR4</span>
+ <span style='color:#006e28;'>`OR1200_DU_DVR4</span>:
+ spr_dat_o = dvr4;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR5</span>
+ <span style='color:#006e28;'>`OR1200_DU_DVR5</span>:
+ spr_dat_o = dvr5;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR6</span>
+ <span style='color:#006e28;'>`OR1200_DU_DVR6</span>:
+ spr_dat_o = dvr6;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DVR7</span>
+ <span style='color:#006e28;'>`OR1200_DU_DVR7</span>:
+ spr_dat_o = dvr7;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR0</span>
+ <span style='color:#006e28;'>`OR1200_DU_DCR0</span>:
+ spr_dat_o = {<span style='color:#b08000;'>24'h00_0000</span>, dcr0};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR1</span>
+ <span style='color:#006e28;'>`OR1200_DU_DCR1</span>:
+ spr_dat_o = {<span style='color:#b08000;'>24'h00_0000</span>, dcr1};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR2</span>
+ <span style='color:#006e28;'>`OR1200_DU_DCR2</span>:
+ spr_dat_o = {<span style='color:#b08000;'>24'h00_0000</span>, dcr2};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR3</span>
+ <span style='color:#006e28;'>`OR1200_DU_DCR3</span>:
+ spr_dat_o = {<span style='color:#b08000;'>24'h00_0000</span>, dcr3};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR4</span>
+ <span style='color:#006e28;'>`OR1200_DU_DCR4</span>:
+ spr_dat_o = {<span style='color:#b08000;'>24'h00_0000</span>, dcr4};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR5</span>
+ <span style='color:#006e28;'>`OR1200_DU_DCR5</span>:
+ spr_dat_o = {<span style='color:#b08000;'>24'h00_0000</span>, dcr5};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR6</span>
+ <span style='color:#006e28;'>`OR1200_DU_DCR6</span>:
+ spr_dat_o = {<span style='color:#b08000;'>24'h00_0000</span>, dcr6};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DCR7</span>
+ <span style='color:#006e28;'>`OR1200_DU_DCR7</span>:
+ spr_dat_o = {<span style='color:#b08000;'>24'h00_0000</span>, dcr7};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DMR1</span>
+ <span style='color:#006e28;'>`OR1200_DU_DMR1</span>:
+ spr_dat_o = {<span style='color:#b08000;'>7'h00</span>, dmr1};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DMR2</span>
+ <span style='color:#006e28;'>`OR1200_DU_DMR2</span>:
+ spr_dat_o = {<span style='color:#b08000;'>8'h00</span>, dmr2};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DWCR0</span>
+ <span style='color:#006e28;'>`OR1200_DU_DWCR0</span>:
+ spr_dat_o = dwcr0;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DWCR1</span>
+ <span style='color:#006e28;'>`OR1200_DU_DWCR1</span>:
+ spr_dat_o = dwcr1;
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DSR</span>
+ <span style='color:#006e28;'>`OR1200_DU_DSR</span>:
+ spr_dat_o = {<span style='color:#b08000;'>18'b0</span>, dsr};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_DRR</span>
+ <span style='color:#006e28;'>`OR1200_DU_DRR</span>:
+ spr_dat_o = {<span style='color:#b08000;'>18'b0</span>, drr};
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_TB_IMPLEMENTED</span>
+ <span style='color:#006e28;'>`OR1200_DU_TBADR</span>:
+ spr_dat_o = {<span style='color:#b08000;'>24'h000000</span>, tb_wadr};
+ <span style='color:#006e28;'>`OR1200_DU_TBIA</span>:
+ spr_dat_o = tbia_dat_o;
+ <span style='color:#006e28;'>`OR1200_DU_TBIM</span>:
+ spr_dat_o = tbim_dat_o;
+ <span style='color:#006e28;'>`OR1200_DU_TBAR</span>:
+ spr_dat_o = tbar_dat_o;
+ <span style='color:#006e28;'>`OR1200_DU_TBTS</span>:
+ spr_dat_o = tbts_dat_o;
+<span style='color:#006e28;'>`endif</span>
+ <b>default</b>:
+ spr_dat_o = <span style='color:#b08000;'>32'h0000_0000</span>;
+ <b>endcase</b>
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// DSR alias</span>
+<span style='color:#898887;'>//</span>
+<b>assign</b> du_dsr = dsr;
+
+<span style='color:#006e28;'>`ifdef OR1200_DU_HWBKPTS</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Compare To What (Match Condition 0)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr0 <span style='color:#0057ae;'>or</span> id_pc <span \
style='color:#0057ae;'>or</span> dcpu_adr_i <span style='color:#0057ae;'>or</span> \
dcpu_dat_dc + <span style='color:#0057ae;'>or</span> dcpu_dat_lsu <span \
style='color:#0057ae;'>or</span> dcpu_we_i) + <b>case</b> (dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span style='color:#898887;'>// \
synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b001</span>: match_cond0_ct = id_pc; <span \
style='color:#898887;'>// insn fetch EA</span> + <span \
style='color:#b08000;'>3'b010</span>: match_cond0_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load EA</span> + <span \
style='color:#b08000;'>3'b011</span>: match_cond0_ct = dcpu_adr_i; <span \
style='color:#898887;'>// store EA</span> + <span \
style='color:#b08000;'>3'b100</span>: match_cond0_ct = dcpu_dat_dc; <span \
style='color:#898887;'>// load data</span> + <span \
style='color:#b08000;'>3'b101</span>: match_cond0_ct = dcpu_dat_lsu; <span \
style='color:#898887;'>// store data</span> + <span \
style='color:#b08000;'>3'b110</span>: match_cond0_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load/store EA</span> + <b>default</b>:match_cond0_ct = \
dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// When To Compare (Match Condition 0)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr0 <span style='color:#0057ae;'>or</span> dcpu_cycstb_i)
+ <b>case</b> (dcr0[<span style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span \
style='color:#898887;'>// synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b000</span>: match_cond0_stb = <span \
style='color:#b08000;'>1'b0</span>; <span style='color:#898887;'>//comparison \
disabled</span> + <span style='color:#b08000;'>3'b001</span>: match_cond0_stb = \
<span style='color:#b08000;'>1'b1</span>; <span style='color:#898887;'>// insn fetch \
EA</span> + <b>default</b>:match_cond0_stb = dcpu_cycstb_i; <span \
style='color:#898887;'>// any load/store</span> + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Match Condition 0</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(match_cond0_stb <span style='color:#0057ae;'>or</span> dcr0 <span \
style='color:#0057ae;'>or</span> dvr0 <span style='color:#0057ae;'>or</span> \
match_cond0_ct) + <b>casex</b> ({match_cond0_stb, dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CC</span>]}) + <span \
style='color:#b08000;'>4'b0_xxx</span>, + <span \
style='color:#b08000;'>4'b1_000</span>, + <span \
style='color:#b08000;'>4'b1_111</span>: match0 = <span \
style='color:#b08000;'>1'b0</span>; + <span style='color:#b08000;'>4'b1_001</span>: \
match0 = + ({(match_cond0_ct[<span style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond0_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} == + \
{(dvr0[<span style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr0[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_010</span>: match0 = + ({(match_cond0_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond0_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} < + \
{(dvr0[<span style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr0[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_011</span>: match0 = + ({(match_cond0_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond0_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} <= + \
{(dvr0[<span style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr0[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_100</span>: match0 = + ({(match_cond0_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond0_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} > + \
{(dvr0[<span style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr0[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_101</span>: match0 = + ({(match_cond0_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond0_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} >= + \
{(dvr0[<span style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr0[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_110</span>: match0 = + ({(match_cond0_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond0_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} != + \
{(dvr0[<span style='color:#b08000;'>31</span>] ^ dcr0[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr0[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 0</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> match0)
+ <b>case</b> (dmr1[<span style='color:#006e28;'>`OR1200_DU_DMR1_CW0</span>])
+ <span style='color:#b08000;'>2'b00</span>: wp[<span \
style='color:#b08000;'>0</span>] = match0; + <span \
style='color:#b08000;'>2'b01</span>: wp[<span style='color:#b08000;'>0</span>] = \
match0; + <span style='color:#b08000;'>2'b10</span>: wp[<span \
style='color:#b08000;'>0</span>] = match0; + <span \
style='color:#b08000;'>2'b11</span>: wp[<span style='color:#b08000;'>0</span>] = \
<span style='color:#b08000;'>1'b0</span>; + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Compare To What (Match Condition 1)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr1 <span style='color:#0057ae;'>or</span> id_pc <span \
style='color:#0057ae;'>or</span> dcpu_adr_i <span style='color:#0057ae;'>or</span> \
dcpu_dat_dc + <span style='color:#0057ae;'>or</span> dcpu_dat_lsu <span \
style='color:#0057ae;'>or</span> dcpu_we_i) + <b>case</b> (dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span style='color:#898887;'>// \
synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b001</span>: match_cond1_ct = id_pc; <span \
style='color:#898887;'>// insn fetch EA</span> + <span \
style='color:#b08000;'>3'b010</span>: match_cond1_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load EA</span> + <span \
style='color:#b08000;'>3'b011</span>: match_cond1_ct = dcpu_adr_i; <span \
style='color:#898887;'>// store EA</span> + <span \
style='color:#b08000;'>3'b100</span>: match_cond1_ct = dcpu_dat_dc; <span \
style='color:#898887;'>// load data</span> + <span \
style='color:#b08000;'>3'b101</span>: match_cond1_ct = dcpu_dat_lsu; <span \
style='color:#898887;'>// store data</span> + <span \
style='color:#b08000;'>3'b110</span>: match_cond1_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load/store EA</span> + <b>default</b>:match_cond1_ct = \
dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// When To Compare (Match Condition 1)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr1 <span style='color:#0057ae;'>or</span> dcpu_cycstb_i)
+ <b>case</b> (dcr1[<span style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span \
style='color:#898887;'>// synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b000</span>: match_cond1_stb = <span \
style='color:#b08000;'>1'b0</span>; <span style='color:#898887;'>//comparison \
disabled</span> + <span style='color:#b08000;'>3'b001</span>: match_cond1_stb = \
<span style='color:#b08000;'>1'b1</span>; <span style='color:#898887;'>// insn fetch \
EA</span> + <b>default</b>:match_cond1_stb = dcpu_cycstb_i; <span \
style='color:#898887;'>// any load/store</span> + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Match Condition 1</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(match_cond1_stb <span style='color:#0057ae;'>or</span> dcr1 <span \
style='color:#0057ae;'>or</span> dvr1 <span style='color:#0057ae;'>or</span> \
match_cond1_ct) + <b>casex</b> ({match_cond1_stb, dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CC</span>]}) + <span \
style='color:#b08000;'>4'b0_xxx</span>, + <span \
style='color:#b08000;'>4'b1_000</span>, + <span \
style='color:#b08000;'>4'b1_111</span>: match1 = <span \
style='color:#b08000;'>1'b0</span>; + <span style='color:#b08000;'>4'b1_001</span>: \
match1 = + ({(match_cond1_ct[<span style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond1_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} == + \
{(dvr1[<span style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr1[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_010</span>: match1 = + ({(match_cond1_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond1_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} < + \
{(dvr1[<span style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr1[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_011</span>: match1 = + ({(match_cond1_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond1_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} <= + \
{(dvr1[<span style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr1[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_100</span>: match1 = + ({(match_cond1_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond1_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} > + \
{(dvr1[<span style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr1[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_101</span>: match1 = + ({(match_cond1_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond1_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} >= + \
{(dvr1[<span style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr1[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_110</span>: match1 = + ({(match_cond1_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond1_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} != + \
{(dvr1[<span style='color:#b08000;'>31</span>] ^ dcr1[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr1[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 1</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> match1 <span \
style='color:#0057ae;'>or</span> wp) + <b>case</b> (dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_CW1</span>]) + <span \
style='color:#b08000;'>2'b00</span>: wp[<span style='color:#b08000;'>1</span>] = \
match1; + <span style='color:#b08000;'>2'b01</span>: wp[<span \
style='color:#b08000;'>1</span>] = match1 & wp[<span \
style='color:#b08000;'>0</span>]; + <span style='color:#b08000;'>2'b10</span>: \
wp[<span style='color:#b08000;'>1</span>] = match1 | wp[<span \
style='color:#b08000;'>0</span>]; + <span style='color:#b08000;'>2'b11</span>: \
wp[<span style='color:#b08000;'>1</span>] = <span style='color:#b08000;'>1'b0</span>; \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Compare To What (Match Condition 2)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr2 <span style='color:#0057ae;'>or</span> id_pc <span \
style='color:#0057ae;'>or</span> dcpu_adr_i <span style='color:#0057ae;'>or</span> \
dcpu_dat_dc + <span style='color:#0057ae;'>or</span> dcpu_dat_lsu <span \
style='color:#0057ae;'>or</span> dcpu_we_i) + <b>case</b> (dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span style='color:#898887;'>// \
synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b001</span>: match_cond2_ct = id_pc; <span \
style='color:#898887;'>// insn fetch EA</span> + <span \
style='color:#b08000;'>3'b010</span>: match_cond2_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load EA</span> + <span \
style='color:#b08000;'>3'b011</span>: match_cond2_ct = dcpu_adr_i; <span \
style='color:#898887;'>// store EA</span> + <span \
style='color:#b08000;'>3'b100</span>: match_cond2_ct = dcpu_dat_dc; <span \
style='color:#898887;'>// load data</span> + <span \
style='color:#b08000;'>3'b101</span>: match_cond2_ct = dcpu_dat_lsu; <span \
style='color:#898887;'>// store data</span> + <span \
style='color:#b08000;'>3'b110</span>: match_cond2_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load/store EA</span> + <b>default</b>:match_cond2_ct = \
dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// When To Compare (Match Condition 2)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr2 <span style='color:#0057ae;'>or</span> dcpu_cycstb_i)
+ <b>case</b> (dcr2[<span style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span \
style='color:#898887;'>// synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b000</span>: match_cond2_stb = <span \
style='color:#b08000;'>1'b0</span>; <span style='color:#898887;'>//comparison \
disabled</span> + <span style='color:#b08000;'>3'b001</span>: match_cond2_stb = \
<span style='color:#b08000;'>1'b1</span>; <span style='color:#898887;'>// insn fetch \
EA</span> + <b>default</b>:match_cond2_stb = dcpu_cycstb_i; <span \
style='color:#898887;'>// any load/store</span> + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Match Condition 2</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(match_cond2_stb <span style='color:#0057ae;'>or</span> dcr2 <span \
style='color:#0057ae;'>or</span> dvr2 <span style='color:#0057ae;'>or</span> \
match_cond2_ct) + <b>casex</b> ({match_cond2_stb, dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CC</span>]}) + <span \
style='color:#b08000;'>4'b0_xxx</span>, + <span \
style='color:#b08000;'>4'b1_000</span>, + <span \
style='color:#b08000;'>4'b1_111</span>: match2 = <span \
style='color:#b08000;'>1'b0</span>; + <span style='color:#b08000;'>4'b1_001</span>: \
match2 = + ({(match_cond2_ct[<span style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond2_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} == + \
{(dvr2[<span style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr2[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_010</span>: match2 = + ({(match_cond2_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond2_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} < + \
{(dvr2[<span style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr2[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_011</span>: match2 = + ({(match_cond2_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond2_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} <= + \
{(dvr2[<span style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr2[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_100</span>: match2 = + ({(match_cond2_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond2_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} > + \
{(dvr2[<span style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr2[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_101</span>: match2 = + ({(match_cond2_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond2_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} >= + \
{(dvr2[<span style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr2[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_110</span>: match2 = + ({(match_cond2_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond2_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} != + \
{(dvr2[<span style='color:#b08000;'>31</span>] ^ dcr2[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr2[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 2</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> match2 <span \
style='color:#0057ae;'>or</span> wp) + <b>case</b> (dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_CW2</span>]) + <span \
style='color:#b08000;'>2'b00</span>: wp[<span style='color:#b08000;'>2</span>] = \
match2; + <span style='color:#b08000;'>2'b01</span>: wp[<span \
style='color:#b08000;'>2</span>] = match2 & wp[<span \
style='color:#b08000;'>1</span>]; + <span style='color:#b08000;'>2'b10</span>: \
wp[<span style='color:#b08000;'>2</span>] = match2 | wp[<span \
style='color:#b08000;'>1</span>]; + <span style='color:#b08000;'>2'b11</span>: \
wp[<span style='color:#b08000;'>2</span>] = <span style='color:#b08000;'>1'b0</span>; \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Compare To What (Match Condition 3)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr3 <span style='color:#0057ae;'>or</span> id_pc <span \
style='color:#0057ae;'>or</span> dcpu_adr_i <span style='color:#0057ae;'>or</span> \
dcpu_dat_dc + <span style='color:#0057ae;'>or</span> dcpu_dat_lsu <span \
style='color:#0057ae;'>or</span> dcpu_we_i) + <b>case</b> (dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span style='color:#898887;'>// \
synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b001</span>: match_cond3_ct = id_pc; <span \
style='color:#898887;'>// insn fetch EA</span> + <span \
style='color:#b08000;'>3'b010</span>: match_cond3_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load EA</span> + <span \
style='color:#b08000;'>3'b011</span>: match_cond3_ct = dcpu_adr_i; <span \
style='color:#898887;'>// store EA</span> + <span \
style='color:#b08000;'>3'b100</span>: match_cond3_ct = dcpu_dat_dc; <span \
style='color:#898887;'>// load data</span> + <span \
style='color:#b08000;'>3'b101</span>: match_cond3_ct = dcpu_dat_lsu; <span \
style='color:#898887;'>// store data</span> + <span \
style='color:#b08000;'>3'b110</span>: match_cond3_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load/store EA</span> + <b>default</b>:match_cond3_ct = \
dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// When To Compare (Match Condition 3)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr3 <span style='color:#0057ae;'>or</span> dcpu_cycstb_i)
+ <b>case</b> (dcr3[<span style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span \
style='color:#898887;'>// synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b000</span>: match_cond3_stb = <span \
style='color:#b08000;'>1'b0</span>; <span style='color:#898887;'>//comparison \
disabled</span> + <span style='color:#b08000;'>3'b001</span>: match_cond3_stb = \
<span style='color:#b08000;'>1'b1</span>; <span style='color:#898887;'>// insn fetch \
EA</span> + <b>default</b>:match_cond3_stb = dcpu_cycstb_i; <span \
style='color:#898887;'>// any load/store</span> + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Match Condition 3</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(match_cond3_stb <span style='color:#0057ae;'>or</span> dcr3 <span \
style='color:#0057ae;'>or</span> dvr3 <span style='color:#0057ae;'>or</span> \
match_cond3_ct) + <b>casex</b> ({match_cond3_stb, dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CC</span>]}) + <span \
style='color:#b08000;'>4'b0_xxx</span>, + <span \
style='color:#b08000;'>4'b1_000</span>, + <span \
style='color:#b08000;'>4'b1_111</span>: match3 = <span \
style='color:#b08000;'>1'b0</span>; + <span style='color:#b08000;'>4'b1_001</span>: \
match3 = + ({(match_cond3_ct[<span style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond3_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} == + \
{(dvr3[<span style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr3[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_010</span>: match3 = + ({(match_cond3_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond3_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} < + \
{(dvr3[<span style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr3[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_011</span>: match3 = + ({(match_cond3_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond3_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} <= + \
{(dvr3[<span style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr3[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_100</span>: match3 = + ({(match_cond3_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond3_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} > + \
{(dvr3[<span style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr3[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_101</span>: match3 = + ({(match_cond3_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond3_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} >= + \
{(dvr3[<span style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr3[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_110</span>: match3 = + ({(match_cond3_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond3_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} != + \
{(dvr3[<span style='color:#b08000;'>31</span>] ^ dcr3[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr3[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 3</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> match3 <span \
style='color:#0057ae;'>or</span> wp) + <b>case</b> (dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_CW3</span>]) + <span \
style='color:#b08000;'>2'b00</span>: wp[<span style='color:#b08000;'>3</span>] = \
match3; + <span style='color:#b08000;'>2'b01</span>: wp[<span \
style='color:#b08000;'>3</span>] = match3 & wp[<span \
style='color:#b08000;'>2</span>]; + <span style='color:#b08000;'>2'b10</span>: \
wp[<span style='color:#b08000;'>3</span>] = match3 | wp[<span \
style='color:#b08000;'>2</span>]; + <span style='color:#b08000;'>2'b11</span>: \
wp[<span style='color:#b08000;'>3</span>] = <span style='color:#b08000;'>1'b0</span>; \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Compare To What (Match Condition 4)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr4 <span style='color:#0057ae;'>or</span> id_pc <span \
style='color:#0057ae;'>or</span> dcpu_adr_i <span style='color:#0057ae;'>or</span> \
dcpu_dat_dc + <span style='color:#0057ae;'>or</span> dcpu_dat_lsu <span \
style='color:#0057ae;'>or</span> dcpu_we_i) + <b>case</b> (dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span style='color:#898887;'>// \
synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b001</span>: match_cond4_ct = id_pc; <span \
style='color:#898887;'>// insn fetch EA</span> + <span \
style='color:#b08000;'>3'b010</span>: match_cond4_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load EA</span> + <span \
style='color:#b08000;'>3'b011</span>: match_cond4_ct = dcpu_adr_i; <span \
style='color:#898887;'>// store EA</span> + <span \
style='color:#b08000;'>3'b100</span>: match_cond4_ct = dcpu_dat_dc; <span \
style='color:#898887;'>// load data</span> + <span \
style='color:#b08000;'>3'b101</span>: match_cond4_ct = dcpu_dat_lsu; <span \
style='color:#898887;'>// store data</span> + <span \
style='color:#b08000;'>3'b110</span>: match_cond4_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load/store EA</span> + <b>default</b>:match_cond4_ct = \
dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// When To Compare (Match Condition 4)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr4 <span style='color:#0057ae;'>or</span> dcpu_cycstb_i)
+ <b>case</b> (dcr4[<span style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span \
style='color:#898887;'>// synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b000</span>: match_cond4_stb = <span \
style='color:#b08000;'>1'b0</span>; <span style='color:#898887;'>//comparison \
disabled</span> + <span style='color:#b08000;'>3'b001</span>: match_cond4_stb = \
<span style='color:#b08000;'>1'b1</span>; <span style='color:#898887;'>// insn fetch \
EA</span> + <b>default</b>:match_cond4_stb = dcpu_cycstb_i; <span \
style='color:#898887;'>// any load/store</span> + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Match Condition 4</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(match_cond4_stb <span style='color:#0057ae;'>or</span> dcr4 <span \
style='color:#0057ae;'>or</span> dvr4 <span style='color:#0057ae;'>or</span> \
match_cond4_ct) + <b>casex</b> ({match_cond4_stb, dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CC</span>]}) + <span \
style='color:#b08000;'>4'b0_xxx</span>, + <span \
style='color:#b08000;'>4'b1_000</span>, + <span \
style='color:#b08000;'>4'b1_111</span>: match4 = <span \
style='color:#b08000;'>1'b0</span>; + <span style='color:#b08000;'>4'b1_001</span>: \
match4 = + ({(match_cond4_ct[<span style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond4_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} == + \
{(dvr4[<span style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr4[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_010</span>: match4 = + ({(match_cond4_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond4_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} < + \
{(dvr4[<span style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr4[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_011</span>: match4 = + ({(match_cond4_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond4_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} <= + \
{(dvr4[<span style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr4[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_100</span>: match4 = + ({(match_cond4_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond4_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} > + \
{(dvr4[<span style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr4[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_101</span>: match4 = + ({(match_cond4_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond4_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} >= + \
{(dvr4[<span style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr4[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_110</span>: match4 = + ({(match_cond4_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond4_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} != + \
{(dvr4[<span style='color:#b08000;'>31</span>] ^ dcr4[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr4[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 4</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> match4 <span \
style='color:#0057ae;'>or</span> wp) + <b>case</b> (dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_CW4</span>]) + <span \
style='color:#b08000;'>2'b00</span>: wp[<span style='color:#b08000;'>4</span>] = \
match4; + <span style='color:#b08000;'>2'b01</span>: wp[<span \
style='color:#b08000;'>4</span>] = match4 & wp[<span \
style='color:#b08000;'>3</span>]; + <span style='color:#b08000;'>2'b10</span>: \
wp[<span style='color:#b08000;'>4</span>] = match4 | wp[<span \
style='color:#b08000;'>3</span>]; + <span style='color:#b08000;'>2'b11</span>: \
wp[<span style='color:#b08000;'>4</span>] = <span style='color:#b08000;'>1'b0</span>; \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Compare To What (Match Condition 5)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr5 <span style='color:#0057ae;'>or</span> id_pc <span \
style='color:#0057ae;'>or</span> dcpu_adr_i <span style='color:#0057ae;'>or</span> \
dcpu_dat_dc + <span style='color:#0057ae;'>or</span> dcpu_dat_lsu <span \
style='color:#0057ae;'>or</span> dcpu_we_i) + <b>case</b> (dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span style='color:#898887;'>// \
synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b001</span>: match_cond5_ct = id_pc; <span \
style='color:#898887;'>// insn fetch EA</span> + <span \
style='color:#b08000;'>3'b010</span>: match_cond5_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load EA</span> + <span \
style='color:#b08000;'>3'b011</span>: match_cond5_ct = dcpu_adr_i; <span \
style='color:#898887;'>// store EA</span> + <span \
style='color:#b08000;'>3'b100</span>: match_cond5_ct = dcpu_dat_dc; <span \
style='color:#898887;'>// load data</span> + <span \
style='color:#b08000;'>3'b101</span>: match_cond5_ct = dcpu_dat_lsu; <span \
style='color:#898887;'>// store data</span> + <span \
style='color:#b08000;'>3'b110</span>: match_cond5_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load/store EA</span> + <b>default</b>:match_cond5_ct = \
dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// When To Compare (Match Condition 5)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr5 <span style='color:#0057ae;'>or</span> dcpu_cycstb_i)
+ <b>case</b> (dcr5[<span style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span \
style='color:#898887;'>// synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b000</span>: match_cond5_stb = <span \
style='color:#b08000;'>1'b0</span>; <span style='color:#898887;'>//comparison \
disabled</span> + <span style='color:#b08000;'>3'b001</span>: match_cond5_stb = \
<span style='color:#b08000;'>1'b1</span>; <span style='color:#898887;'>// insn fetch \
EA</span> + <b>default</b>:match_cond5_stb = dcpu_cycstb_i; <span \
style='color:#898887;'>// any load/store</span> + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Match Condition 5</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(match_cond5_stb <span style='color:#0057ae;'>or</span> dcr5 <span \
style='color:#0057ae;'>or</span> dvr5 <span style='color:#0057ae;'>or</span> \
match_cond5_ct) + <b>casex</b> ({match_cond5_stb, dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CC</span>]}) + <span \
style='color:#b08000;'>4'b0_xxx</span>, + <span \
style='color:#b08000;'>4'b1_000</span>, + <span \
style='color:#b08000;'>4'b1_111</span>: match5 = <span \
style='color:#b08000;'>1'b0</span>; + <span style='color:#b08000;'>4'b1_001</span>: \
match5 = + ({(match_cond5_ct[<span style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond5_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} == + \
{(dvr5[<span style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr5[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_010</span>: match5 = + ({(match_cond5_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond5_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} < + \
{(dvr5[<span style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr5[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_011</span>: match5 = + ({(match_cond5_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond5_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} <= + \
{(dvr5[<span style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr5[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_100</span>: match5 = + ({(match_cond5_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond5_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} > + \
{(dvr5[<span style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr5[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_101</span>: match5 = + ({(match_cond5_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond5_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} >= + \
{(dvr5[<span style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr5[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_110</span>: match5 = + ({(match_cond5_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond5_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} != + \
{(dvr5[<span style='color:#b08000;'>31</span>] ^ dcr5[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr5[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 5</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> match5 <span \
style='color:#0057ae;'>or</span> wp) + <b>case</b> (dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_CW5</span>]) + <span \
style='color:#b08000;'>2'b00</span>: wp[<span style='color:#b08000;'>5</span>] = \
match5; + <span style='color:#b08000;'>2'b01</span>: wp[<span \
style='color:#b08000;'>5</span>] = match5 & wp[<span \
style='color:#b08000;'>4</span>]; + <span style='color:#b08000;'>2'b10</span>: \
wp[<span style='color:#b08000;'>5</span>] = match5 | wp[<span \
style='color:#b08000;'>4</span>]; + <span style='color:#b08000;'>2'b11</span>: \
wp[<span style='color:#b08000;'>5</span>] = <span style='color:#b08000;'>1'b0</span>; \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Compare To What (Match Condition 6)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr6 <span style='color:#0057ae;'>or</span> id_pc <span \
style='color:#0057ae;'>or</span> dcpu_adr_i <span style='color:#0057ae;'>or</span> \
dcpu_dat_dc + <span style='color:#0057ae;'>or</span> dcpu_dat_lsu <span \
style='color:#0057ae;'>or</span> dcpu_we_i) + <b>case</b> (dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span style='color:#898887;'>// \
synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b001</span>: match_cond6_ct = id_pc; <span \
style='color:#898887;'>// insn fetch EA</span> + <span \
style='color:#b08000;'>3'b010</span>: match_cond6_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load EA</span> + <span \
style='color:#b08000;'>3'b011</span>: match_cond6_ct = dcpu_adr_i; <span \
style='color:#898887;'>// store EA</span> + <span \
style='color:#b08000;'>3'b100</span>: match_cond6_ct = dcpu_dat_dc; <span \
style='color:#898887;'>// load data</span> + <span \
style='color:#b08000;'>3'b101</span>: match_cond6_ct = dcpu_dat_lsu; <span \
style='color:#898887;'>// store data</span> + <span \
style='color:#b08000;'>3'b110</span>: match_cond6_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load/store EA</span> + <b>default</b>:match_cond6_ct = \
dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// When To Compare (Match Condition 6)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr6 <span style='color:#0057ae;'>or</span> dcpu_cycstb_i)
+ <b>case</b> (dcr6[<span style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span \
style='color:#898887;'>// synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b000</span>: match_cond6_stb = <span \
style='color:#b08000;'>1'b0</span>; <span style='color:#898887;'>//comparison \
disabled</span> + <span style='color:#b08000;'>3'b001</span>: match_cond6_stb = \
<span style='color:#b08000;'>1'b1</span>; <span style='color:#898887;'>// insn fetch \
EA</span> + <b>default</b>:match_cond6_stb = dcpu_cycstb_i; <span \
style='color:#898887;'>// any load/store</span> + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Match Condition 6</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(match_cond6_stb <span style='color:#0057ae;'>or</span> dcr6 <span \
style='color:#0057ae;'>or</span> dvr6 <span style='color:#0057ae;'>or</span> \
match_cond6_ct) + <b>casex</b> ({match_cond6_stb, dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CC</span>]}) + <span \
style='color:#b08000;'>4'b0_xxx</span>, + <span \
style='color:#b08000;'>4'b1_000</span>, + <span \
style='color:#b08000;'>4'b1_111</span>: match6 = <span \
style='color:#b08000;'>1'b0</span>; + <span style='color:#b08000;'>4'b1_001</span>: \
match6 = + ({(match_cond6_ct[<span style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond6_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} == + \
{(dvr6[<span style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr6[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_010</span>: match6 = + ({(match_cond6_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond6_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} < + \
{(dvr6[<span style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr6[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_011</span>: match6 = + ({(match_cond6_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond6_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} <= + \
{(dvr6[<span style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr6[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_100</span>: match6 = + ({(match_cond6_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond6_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} > + \
{(dvr6[<span style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr6[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_101</span>: match6 = + ({(match_cond6_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond6_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} >= + \
{(dvr6[<span style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr6[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_110</span>: match6 = + ({(match_cond6_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond6_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} != + \
{(dvr6[<span style='color:#b08000;'>31</span>] ^ dcr6[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr6[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 6</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> match6 <span \
style='color:#0057ae;'>or</span> wp) + <b>case</b> (dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_CW6</span>]) + <span \
style='color:#b08000;'>2'b00</span>: wp[<span style='color:#b08000;'>6</span>] = \
match6; + <span style='color:#b08000;'>2'b01</span>: wp[<span \
style='color:#b08000;'>6</span>] = match6 & wp[<span \
style='color:#b08000;'>5</span>]; + <span style='color:#b08000;'>2'b10</span>: \
wp[<span style='color:#b08000;'>6</span>] = match6 | wp[<span \
style='color:#b08000;'>5</span>]; + <span style='color:#b08000;'>2'b11</span>: \
wp[<span style='color:#b08000;'>6</span>] = <span style='color:#b08000;'>1'b0</span>; \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Compare To What (Match Condition 7)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr7 <span style='color:#0057ae;'>or</span> id_pc <span \
style='color:#0057ae;'>or</span> dcpu_adr_i <span style='color:#0057ae;'>or</span> \
dcpu_dat_dc + <span style='color:#0057ae;'>or</span> dcpu_dat_lsu <span \
style='color:#0057ae;'>or</span> dcpu_we_i) + <b>case</b> (dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span style='color:#898887;'>// \
synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b001</span>: match_cond7_ct = id_pc; <span \
style='color:#898887;'>// insn fetch EA</span> + <span \
style='color:#b08000;'>3'b010</span>: match_cond7_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load EA</span> + <span \
style='color:#b08000;'>3'b011</span>: match_cond7_ct = dcpu_adr_i; <span \
style='color:#898887;'>// store EA</span> + <span \
style='color:#b08000;'>3'b100</span>: match_cond7_ct = dcpu_dat_dc; <span \
style='color:#898887;'>// load data</span> + <span \
style='color:#b08000;'>3'b101</span>: match_cond7_ct = dcpu_dat_lsu; <span \
style='color:#898887;'>// store data</span> + <span \
style='color:#b08000;'>3'b110</span>: match_cond7_ct = dcpu_adr_i; <span \
style='color:#898887;'>// load/store EA</span> + <b>default</b>:match_cond7_ct = \
dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// When To Compare (Match Condition 7)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dcr7 <span style='color:#0057ae;'>or</span> dcpu_cycstb_i)
+ <b>case</b> (dcr7[<span style='color:#006e28;'>`OR1200_DU_DCR_CT</span>]) <span \
style='color:#898887;'>// synopsys parallel_case</span> + <span \
style='color:#b08000;'>3'b000</span>: match_cond7_stb = <span \
style='color:#b08000;'>1'b0</span>; <span style='color:#898887;'>//comparison \
disabled</span> + <span style='color:#b08000;'>3'b001</span>: match_cond7_stb = \
<span style='color:#b08000;'>1'b1</span>; <span style='color:#898887;'>// insn fetch \
EA</span> + <b>default</b>:match_cond7_stb = dcpu_cycstb_i; <span \
style='color:#898887;'>// any load/store</span> + <b>endcase</b>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Match Condition 7</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(match_cond7_stb <span style='color:#0057ae;'>or</span> dcr7 <span \
style='color:#0057ae;'>or</span> dvr7 <span style='color:#0057ae;'>or</span> \
match_cond7_ct) + <b>casex</b> ({match_cond7_stb, dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_CC</span>]}) + <span \
style='color:#b08000;'>4'b0_xxx</span>, + <span \
style='color:#b08000;'>4'b1_000</span>, + <span \
style='color:#b08000;'>4'b1_111</span>: match7 = <span \
style='color:#b08000;'>1'b0</span>; + <span style='color:#b08000;'>4'b1_001</span>: \
match7 = + ({(match_cond7_ct[<span style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond7_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} == + \
{(dvr7[<span style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr7[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_010</span>: match7 = + ({(match_cond7_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond7_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} < + \
{(dvr7[<span style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr7[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_011</span>: match7 = + ({(match_cond7_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond7_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} <= + \
{(dvr7[<span style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr7[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_100</span>: match7 = + ({(match_cond7_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond7_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} > + \
{(dvr7[<span style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr7[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_101</span>: match7 = + ({(match_cond7_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond7_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} >= + \
{(dvr7[<span style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr7[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); + <span \
style='color:#b08000;'>4'b1_110</span>: match7 = + ({(match_cond7_ct[<span \
style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), match_cond7_ct[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]} != + \
{(dvr7[<span style='color:#b08000;'>31</span>] ^ dcr7[<span \
style='color:#006e28;'>`OR1200_DU_DCR_SC</span>]), dvr7[<span \
style='color:#b08000;'>30</span>:<span style='color:#b08000;'>0</span>]}); \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 7</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> match7 <span \
style='color:#0057ae;'>or</span> wp) + <b>case</b> (dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_CW7</span>]) + <span \
style='color:#b08000;'>2'b00</span>: wp[<span style='color:#b08000;'>7</span>] = \
match7; + <span style='color:#b08000;'>2'b01</span>: wp[<span \
style='color:#b08000;'>7</span>] = match7 & wp[<span \
style='color:#b08000;'>6</span>]; + <span style='color:#b08000;'>2'b10</span>: \
wp[<span style='color:#b08000;'>7</span>] = match7 | wp[<span \
style='color:#b08000;'>6</span>]; + <span style='color:#b08000;'>2'b11</span>: \
wp[<span style='color:#b08000;'>7</span>] = <span style='color:#b08000;'>1'b0</span>; \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Increment Watchpoint Counter 0</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(wp <span style='color:#0057ae;'>or</span> dmr2)
+ <b>if</b> (dmr2[<span style='color:#006e28;'>`OR1200_DU_DMR2_WCE0</span>])
+ incr_wpcntr0 = |(wp & ~dmr2[<span \
style='color:#006e28;'>`OR1200_DU_DMR2_AWTC</span>]); + <b>else</b>
+ incr_wpcntr0 = <span style='color:#b08000;'>1'b0</span>;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Match Condition Watchpoint Counter 0</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dwcr0)
+ <b>if</b> (dwcr0[<span style='color:#006e28;'>`OR1200_DU_DWCR_MATCH</span>] == \
dwcr0[<span style='color:#006e28;'>`OR1200_DU_DWCR_COUNT</span>]) + wpcntr0_match = \
<span style='color:#b08000;'>1'b1</span>; + <b>else</b>
+ wpcntr0_match = <span style='color:#b08000;'>1'b0</span>;
+
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 8</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> wpcntr0_match <span \
style='color:#0057ae;'>or</span> wp) + <b>case</b> (dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_CW8</span>]) + <span \
style='color:#b08000;'>2'b00</span>: wp[<span style='color:#b08000;'>8</span>] = \
wpcntr0_match; + <span style='color:#b08000;'>2'b01</span>: wp[<span \
style='color:#b08000;'>8</span>] = wpcntr0_match & wp[<span \
style='color:#b08000;'>7</span>]; + <span style='color:#b08000;'>2'b10</span>: \
wp[<span style='color:#b08000;'>8</span>] = wpcntr0_match | wp[<span \
style='color:#b08000;'>7</span>]; + <span style='color:#b08000;'>2'b11</span>: \
wp[<span style='color:#b08000;'>8</span>] = <span style='color:#b08000;'>1'b0</span>; \
+ <b>endcase</b> +
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Increment Watchpoint Counter 1</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(wp <span style='color:#0057ae;'>or</span> dmr2)
+ <b>if</b> (dmr2[<span style='color:#006e28;'>`OR1200_DU_DMR2_WCE1</span>])
+ incr_wpcntr1 = |(wp & dmr2[<span \
style='color:#006e28;'>`OR1200_DU_DMR2_AWTC</span>]); + <b>else</b>
+ incr_wpcntr1 = <span style='color:#b08000;'>1'b0</span>;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Match Condition Watchpoint Counter 1</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dwcr1)
+ <b>if</b> (dwcr1[<span style='color:#006e28;'>`OR1200_DU_DWCR_MATCH</span>] == \
dwcr1[<span style='color:#006e28;'>`OR1200_DU_DWCR_COUNT</span>]) + wpcntr1_match = \
<span style='color:#b08000;'>1'b1</span>; + <b>else</b>
+ wpcntr1_match = <span style='color:#b08000;'>1'b0</span>;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 9</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> wpcntr1_match <span \
style='color:#0057ae;'>or</span> wp) + <b>case</b> (dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_CW9</span>]) + <span \
style='color:#b08000;'>2'b00</span>: wp[<span style='color:#b08000;'>9</span>] = \
wpcntr1_match; + <span style='color:#b08000;'>2'b01</span>: wp[<span \
style='color:#b08000;'>9</span>] = wpcntr1_match & wp[<span \
style='color:#b08000;'>8</span>]; + <span style='color:#b08000;'>2'b10</span>: \
wp[<span style='color:#b08000;'>9</span>] = wpcntr1_match | wp[<span \
style='color:#b08000;'>8</span>]; + <span style='color:#b08000;'>2'b11</span>: \
wp[<span style='color:#b08000;'>9</span>] = <span style='color:#b08000;'>1'b0</span>; \
+ <b>endcase</b> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoint 10</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(dmr1 <span style='color:#0057ae;'>or</span> dbg_ewt_i <span \
style='color:#0057ae;'>or</span> wp) + <b>case</b> (dmr1[<span \
style='color:#006e28;'>`OR1200_DU_DMR1_CW10</span>]) + <span \
style='color:#b08000;'>2'b00</span>: wp[<span style='color:#b08000;'>10</span>] = \
dbg_ewt_i; + <span style='color:#b08000;'>2'b01</span>: wp[<span \
style='color:#b08000;'>10</span>] = dbg_ewt_i & wp[<span \
style='color:#b08000;'>9</span>]; + <span style='color:#b08000;'>2'b10</span>: \
wp[<span style='color:#b08000;'>10</span>] = dbg_ewt_i | wp[<span \
style='color:#b08000;'>9</span>]; + <span style='color:#b08000;'>2'b11</span>: \
wp[<span style='color:#b08000;'>10</span>] = <span \
style='color:#b08000;'>1'b0</span>; + <b>endcase</b>
+
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Watchpoints can cause trap exception</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_HWBKPTS</span>
+<b>assign</b> du_hwbkpt = |(wp & dmr2[<span \
style='color:#006e28;'>`OR1200_DU_DMR2_WGB</span>]) | du_hwbkpt_hold | (dbg_bp_r \
& ~dsr[<span style='color:#006e28;'>`OR1200_DU_DSR_TE</span>]); +<span \
style='color:#006e28;'>`else</span> +<b>assign</b> du_hwbkpt = <span \
style='color:#b08000;'>1'b0</span>; +<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#898887;'>// Hold du_hwbkpt if ex_freeze is active in order to \
cause trap exception </span> +<b>always</b> @(<b>posedge</b> clk <span \
style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + du_hwbkpt_hold <= <span \
style='color:#b08000;'>1'b0</span>; + <b>else</b> <b>if</b> (du_hwbkpt & \
ex_freeze) + du_hwbkpt_hold <= <span style='color:#b08000;'>1'b1</span>;
+ <b>else</b> <b>if</b> (!ex_freeze)
+ du_hwbkpt_hold <= <span style='color:#b08000;'>1'b0</span>;
+
+<span style='color:#006e28;'>`ifdef OR1200_DU_TB_IMPLEMENTED</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Simple trace buffer</span>
+<span style='color:#898887;'>// (right now hardcoded for Xilinx Virtex FPGAs)</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Stores last 256 instruction addresses, \
instruction</span> +<span style='color:#898887;'>// machine words and ALU \
results</span> +<span style='color:#898887;'>//</span>
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Trace buffer write enable</span>
+<span style='color:#898887;'>//</span>
+<b>assign</b> tb_enw = ~ex_freeze & ~((ex_insn[<span \
style='color:#b08000;'>31</span>:<span style='color:#b08000;'>26</span>] == <span \
style='color:#006e28;'>`OR1200_OR32_NOP</span>) & ex_insn[<span \
style='color:#b08000;'>16</span>]); +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Trace buffer write address pointer</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + tb_wadr <= <span \
style='color:#b08000;'>8'h00</span>; + <b>else</b> <b>if</b> (tb_enw)
+ tb_wadr <= tb_wadr + <span style='color:#b08000;'>8'd1</span>;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Free running counter (time stamp)</span>
+<span style='color:#898887;'>//</span>
+<b>always</b> @(<b>posedge</b> clk <span style='color:#0057ae;'>or</span> <span \
style='color:#006e28;'>`OR1200_RST_EVENT</span> rst) + <b>if</b> (rst == <span \
style='color:#006e28;'>`OR1200_RST_VALUE</span>) + tb_timstmp <= <span \
style='color:#b08000;'>32'h00000000</span>; + <b>else</b> <b>if</b> (!dbg_bp_r)
+ tb_timstmp <= tb_timstmp + <span style='color:#b08000;'>32'd1</span>;
+
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Trace buffer RAMs</span>
+<span style='color:#898887;'>//</span>
+
+or1200_dpram_256x32 tbia_ram(
+ .clk_a(clk),
+ .rst_a(<span style='color:#b08000;'>1'b0</span>),
+ .addr_a(spr_addr[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]), + .ce_a(<span style='color:#b08000;'>1'b1</span>),
+ .oe_a(<span style='color:#b08000;'>1'b1</span>),
+ .do_a(tbia_dat_o),
+
+ .clk_b(clk),
+ .rst_b(<span style='color:#b08000;'>1'b0</span>),
+ .addr_b(tb_wadr),
+ .di_b(spr_dat_npc),
+ .ce_b(<span style='color:#b08000;'>1'b1</span>),
+ .we_b(tb_enw)
+
+);
+
+or1200_dpram_256x32 tbim_ram(
+ .clk_a(clk),
+ .rst_a(<span style='color:#b08000;'>1'b0</span>),
+ .addr_a(spr_addr[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]), + .ce_a(<span style='color:#b08000;'>1'b1</span>),
+ .oe_a(<span style='color:#b08000;'>1'b1</span>),
+ .do_a(tbim_dat_o),
+
+ .clk_b(clk),
+ .rst_b(<span style='color:#b08000;'>1'b0</span>),
+ .addr_b(tb_wadr),
+ .di_b(ex_insn),
+ .ce_b(<span style='color:#b08000;'>1'b1</span>),
+ .we_b(tb_enw)
+);
+
+or1200_dpram_256x32 tbar_ram(
+ .clk_a(clk),
+ .rst_a(<span style='color:#b08000;'>1'b0</span>),
+ .addr_a(spr_addr[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]), + .ce_a(<span style='color:#b08000;'>1'b1</span>),
+ .oe_a(<span style='color:#b08000;'>1'b1</span>),
+ .do_a(tbar_dat_o),
+
+ .clk_b(clk),
+ .rst_b(<span style='color:#b08000;'>1'b0</span>),
+ .addr_b(tb_wadr),
+ .di_b(rf_dataw),
+ .ce_b(<span style='color:#b08000;'>1'b1</span>),
+ .we_b(tb_enw)
+);
+
+or1200_dpram_256x32 tbts_ram(
+ .clk_a(clk),
+ .rst_a(<span style='color:#b08000;'>1'b0</span>),
+ .addr_a(spr_addr[<span style='color:#b08000;'>7</span>:<span \
style='color:#b08000;'>0</span>]), + .ce_a(<span style='color:#b08000;'>1'b1</span>),
+ .oe_a(<span style='color:#b08000;'>1'b1</span>),
+ .do_a(tbts_dat_o),
+
+ .clk_b(clk),
+ .rst_b(<span style='color:#b08000;'>1'b0</span>),
+ .addr_b(tb_wadr),
+ .di_b(tb_timstmp),
+ .ce_b(<span style='color:#b08000;'>1'b1</span>),
+ .we_b(tb_enw)
+);
+
+<span style='color:#006e28;'>`else</span>
+
+<b>assign</b> tbia_dat_o = <span style='color:#b08000;'>32'h0000_0000</span>;
+<b>assign</b> tbim_dat_o = <span style='color:#b08000;'>32'h0000_0000</span>;
+<b>assign</b> tbar_dat_o = <span style='color:#b08000;'>32'h0000_0000</span>;
+<b>assign</b> tbts_dat_o = <span style='color:#b08000;'>32'h0000_0000</span>;
+
+<span style='color:#006e28;'>`endif </span><span style='color:#898887;'>// \
OR1200_DU_TB_IMPLEMENTED</span> +
+<span style='color:#006e28;'>`else </span><span style='color:#898887;'>// \
OR1200_DU_IMPLEMENTED</span> +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// When DU is not implemented, drive all outputs as \
would when DU is disabled</span> +<span style='color:#898887;'>//</span>
+<b>assign</b> dbg_bp_o = <span style='color:#b08000;'>1'b0</span>;
+<b>assign</b> du_dsr = {<span \
style='color:#006e28;'>`OR1200_DU_DSR_WIDTH</span>{<span \
style='color:#b08000;'>1'b0</span>}}; +<b>assign</b> du_dmr1 = {<span \
style='color:#b08000;'>25</span>{<span style='color:#b08000;'>1'b0</span>}}; \
+<b>assign</b> du_hwbkpt = <span style='color:#b08000;'>1'b0</span>; +
+<span style='color:#898887;'>//</span>
+<span style='color:#898887;'>// Read DU registers</span>
+<span style='color:#898887;'>//</span>
+<span style='color:#006e28;'>`ifdef OR1200_DU_READREGS</span>
+<b>assign</b> spr_dat_o = <span style='color:#b08000;'>32'h0000_0000</span>;
+<span style='color:#006e28;'>`ifdef OR1200_DU_UNUSED_ZERO</span>
+<span style='color:#006e28;'>`endif</span>
+<span style='color:#006e28;'>`endif</span>
+
+<span style='color:#006e28;'>`endif</span>
+
+<b>endmodule</b>
+</pre>
+</body>
+</html>
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+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "DTD/xhtml1-strict.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
+<meta name="Generator" content="Kate, the KDE Advanced Text Editor" />
+<title>light52_muldiv.vhdl</title>
+</head>
+<body>
+<pre style='color:#1f1c1b;background-color:#ffffff;'>
+<span style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- light52_muldiv.vhdl -- Simple multiplier/divider \
module.</span> +<span \
style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- The 8051 mul and div instructions are both unsigned \
and operands are 8 bit.</span> +<span style='color:#898887;'>--</span>
+<span style='color:#898887;'>-- This module implements the division as a sequential \
state machine which takes</span> +<span style='color:#898887;'>-- 8 cycles to \
complete. </span> +<span style='color:#898887;'>-- The multiplier can be implemented \
as sequential or as combinational, in which</span> +<span style='color:#898887;'>-- \
case it will use a DSP block in those architectures that support it.</span> +<span \
style='color:#898887;'>-- No attempt has been made to make this module generic or \
reusable.</span> +<span style='color:#898887;'>--</span>
+<span style='color:#898887;'>-- If you want a combinational multiplier but don't \
want to waste a DSP block </span> +<span style='color:#898887;'>-- in this module, \
you need to modify this file adding whatever synthesis </span> +<span \
style='color:#898887;'>-- pragmas your tool of choice needs.</span> +<span \
style='color:#898887;'>--</span> +<span style='color:#898887;'>-- Note that unlike \
the division state machine, the combinational product logic</span> +<span \
style='color:#898887;'>-- is always operating: when SEQUENTIAL_MULTIPLIER=true, \
prod_out equals </span> +<span style='color:#898887;'>-- data_a * data_b with a \
latency of 1 clock cycle, and mul_ready is hardwired</span> +<span \
style='color:#898887;'>-- to '1'.</span> +<span style='color:#898887;'>--</span>
+<span style='color:#898887;'>-- FIXME explain division algorithm.</span>
+<span style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- GENERICS:</span>
+<span style='color:#898887;'>-- </span>
+<span style='color:#898887;'>-- SEQUENTIAL_MULTIPLIER -- Sequential vs. \
combinational multiplier.</span> +<span style='color:#898887;'>-- When true, a \
sequential implementation will be used for the multiplier, </span> +<span \
style='color:#898887;'>-- which will usually save a lot of logic or a dedicated \
multiplier.</span> +<span style='color:#898887;'>-- When false, a combinational \
registered multiplier will be used.</span> +<span style='color:#898887;'>--</span>
+<span style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- INTERFACE SIGNALS:</span>
+<span style='color:#898887;'>--</span>
+<span style='color:#898887;'>-- clk : Clock, active rising edge.</span>
+<span style='color:#898887;'>-- reset : Synchronous reset. Clears only the \
control registers not</span> +<span style='color:#898887;'>-- \
visible to the programmer -- not the output registers.</span> +<span \
style='color:#898887;'>-- </span> +<span style='color:#898887;'>-- data_a : \
Numerator input, should be connected to the ACC register.</span> +<span \
style='color:#898887;'>-- data_b : Denominator input, should be connected to \
the B register.</span> +<span style='color:#898887;'>-- start : Assert for 1 \
cycle to start the division state machine</span> +<span style='color:#898887;'>-- \
(and the product if SEQUENTIAL_MULTIPLIER=true);</span> +<span \
style='color:#898887;'>-- </span> +<span style='color:#898887;'>-- prod_out : \
Product output, valid only when mul_ready='1'.</span> +<span \
style='color:#898887;'>-- quot_out : Quotient output, valid only when \
div_ready='1'.</span> +<span style='color:#898887;'>-- rem_out : Remainder \
output, valid only when div_ready='1'.</span> +<span style='color:#898887;'>-- \
div_ov_out : Division overflow flag, valid only when div_ready='1'.</span> +<span \
style='color:#898887;'>-- mul_ov_out : Product overflow flag, valid only when \
mul_ready='1'.</span> +<span style='color:#898887;'>-- </span>
+<span style='color:#898887;'>-- mul_ready : Asserted permanently if \
SEQUENTIAL_MULTIPLIER=false.</span> +<span style='color:#898887;'>-- div_ready : \
Deasserted the cycle after start is asserted.</span> +<span style='color:#898887;'>-- \
Asserted when the division has completed.</span> +<span \
style='color:#898887;'>--</span> +<span \
style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- Copyright (C) 2012 Jose A. Ruiz</span>
+<span style='color:#898887;'>-- \
</span> +<span style='color:#898887;'>-- This source file may be used and distributed \
without </span> +<span style='color:#898887;'>-- restriction provided that \
this copyright statement is not </span> +<span style='color:#898887;'>-- removed \
from the file and that any derivative work contains </span> +<span \
style='color:#898887;'>-- the original copyright notice and the associated \
disclaimer. </span> +<span style='color:#898887;'>-- \
</span> +<span style='color:#898887;'>-- This source file is free software; you can \
redistribute it </span> +<span style='color:#898887;'>-- and/or modify it under the \
terms of the GNU Lesser General </span> +<span style='color:#898887;'>-- Public \
License as published by the Free Software Foundation; </span> +<span \
style='color:#898887;'>-- either version 2.1 of the License, or (at your option) any \
</span> +<span style='color:#898887;'>-- later version. \
</span> +<span style='color:#898887;'>-- \
</span> +<span style='color:#898887;'>-- This source is distributed in the hope that \
it will be </span> +<span style='color:#898887;'>-- useful, but WITHOUT ANY \
WARRANTY; without even the implied </span> +<span style='color:#898887;'>-- \
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR </span> +<span \
style='color:#898887;'>-- PURPOSE. See the GNU Lesser General Public License for \
more </span> +<span style='color:#898887;'>-- details. \
</span> +<span style='color:#898887;'>-- \
</span> +<span style='color:#898887;'>-- You should have received a copy of the GNU \
Lesser General </span> +<span style='color:#898887;'>-- Public License along with \
this source; if not, download it </span> +<span style='color:#898887;'>-- from \
http://www.opencores.org/lgpl.shtml</span> +<span \
style='color:#898887;'>--------------------------------------------------------------------------------</span>
+
+<b>library</b> ieee;
+<b>use</b> ieee<span style='color:#006e28;'>.</span>std_logic_1164<span \
style='color:#006e28;'>.</span>all; +<b>use</b> ieee<span \
style='color:#006e28;'>.</span>numeric_std<span style='color:#006e28;'>.</span>all; +
+<b>use</b> work<span style='color:#006e28;'>.</span>light52_pkg<span \
style='color:#006e28;'>.</span>all; +<b>use</b> work<span \
style='color:#006e28;'>.</span>light52_ucode_pkg<span \
style='color:#006e28;'>.</span>all; +
+<b><span style='color:#223388;'>entity</span></b> <b><span \
style='color:#bb6600;'>light52_muldiv</span></b> <b>is</b> + <b><span \
style='color:#223388;'>generic</span></b> ( + SEQUENTIAL_MULTIPLIER <span \
style='color:#006e28;'>:</span> <span style='color:#0057ae;'>boolean</span> <span \
style='color:#006e28;'>:=</span> false + );
+ <b><span style='color:#223388;'>port</span></b>(
+ clk <span style='color:#006e28;'>:</span> <b>in</b> <span \
style='color:#0057ae;'>std_logic</span>; + reset <span \
style='color:#006e28;'>:</span> <b>in</b> <span \
style='color:#0057ae;'>std_logic</span>; +
+ data_a <span style='color:#006e28;'>:</span> <b>in</b> \
t_byte; + data_b <span style='color:#006e28;'>:</span> \
<b>in</b> t_byte; + start <span style='color:#006e28;'>:</span> \
<b>in</b> <span style='color:#0057ae;'>std_logic</span>; +
+ prod_out <span style='color:#006e28;'>:</span> <b>out</b> \
t_word; + quot_out <span style='color:#006e28;'>:</span> \
<b>out</b> t_byte; + rem_out <span style='color:#006e28;'>:</span> \
<b>out</b> t_byte; + div_ov_out <span style='color:#006e28;'>:</span> \
<b>out</b> <span style='color:#0057ae;'>std_logic</span>; + mul_ov_out <span \
style='color:#006e28;'>:</span> <b>out</b> <span \
style='color:#0057ae;'>std_logic</span>; +
+ mul_ready <span style='color:#006e28;'>:</span> <b>out</b> <span \
style='color:#0057ae;'>std_logic</span>; + div_ready <span \
style='color:#006e28;'>:</span> <b>out</b> <span \
style='color:#0057ae;'>std_logic</span> + );
+<b><span style='color:#223388;'>end entity light52_muldiv;</span></b>
+
+<b><span style='color:#223388;'>architecture</span></b> <b><span \
style='color:#bb6600;'>sequential</span></b> <b>of</b> <span \
style='color:#644a9b;'>light52_muldiv</span> <b>is</b> +
+<span style='color:#006e28;'>signal</span> bit_ctr <span \
style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>integer</span> <b>range</b> <span \
style='color:#b08000;'>0</span> <span style='color:#006e28;'>to</span> <span \
style='color:#b08000;'>8</span>; +
+<span style='color:#006e28;'>signal</span> b_shift_reg <span \
style='color:#006e28;'>:</span> t_word; +
+<span style='color:#006e28;'>signal</span> den_ge_256 <span \
style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic</span>; +<span style='color:#006e28;'>signal</span> \
num_ge_den <span style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic</span>; +<span style='color:#006e28;'>signal</span> \
sub_num <span style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic</span>; +
+<span style='color:#006e28;'>signal</span> denominator <span \
style='color:#006e28;'>:</span> t_byte; +<span \
style='color:#006e28;'>signal</span> rem_reg <span style='color:#006e28;'>:</span> \
t_byte; +<span style='color:#006e28;'>signal</span> quot_reg <span \
style='color:#006e28;'>:</span> t_byte; +<span \
style='color:#006e28;'>signal</span> prod_reg <span style='color:#006e28;'>:</span> \
t_word; +<span style='color:#006e28;'>signal</span> ready <span \
style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic</span>; +
+<span style='color:#006e28;'>signal</span> load_regs <span \
style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic</span>; +
+<b><span style='color:#223388;'>begin</span></b>
+
+<span style='color:#898887;'>-- Control logic \
---------------------------------------------------------------</span> +
+control_counter<span style='color:#006e28;'>:</span>
+<b><span style='color:#0099aa;'>process</span></b>(clk)
+<b><span style='color:#0099aa;'>begin</span></b>
+ <b><span style='color:#223388;'>if</span></b> clk<span \
style='color:#b08000;'>'event</span> <b>and</b> clk<span \
style='color:#006e28;'>=</span><span style='color:#b08000;'>'1'</span> <b><span \
style='color:#223388;'>then</span></b> + <b><span \
style='color:#223388;'>if</span></b> reset<span style='color:#006e28;'>=</span><span \
style='color:#b08000;'>'1'</span> <b><span style='color:#223388;'>then</span></b> + \
bit_ctr <span style='color:#006e28;'><=</span> <span \
style='color:#b08000;'>8</span>; + <b><span \
style='color:#223388;'>else</span></b> + <b><span \
style='color:#223388;'>if</span></b> load_regs<span \
style='color:#006e28;'>=</span><span style='color:#b08000;'>'1'</span> <b><span \
style='color:#223388;'>then</span></b> + bit_ctr <span \
style='color:#006e28;'><=</span> <span style='color:#b08000;'>0</span>; + \
<b><span style='color:#223388;'>elsif</span></b> bit_ctr <span \
style='color:#006e28;'>/=</span> <span style='color:#b08000;'>8</span> <b><span \
style='color:#223388;'>then</span></b> + bit_ctr <span \
style='color:#006e28;'><=</span> bit_ctr <span style='color:#006e28;'>+</span> \
<span style='color:#b08000;'>1</span>; + <b><span \
style='color:#223388;'>end if;</span></b> + <b><span \
style='color:#223388;'>end if;</span></b> + <b><span style='color:#223388;'>end \
if;</span></b> +<b><span style='color:#0099aa;'>end process \
</span></b>control_counter; +
+<span style='color:#898887;'>-- Internal signal ready is asserted after 8 \
cycles.</span> +<span style='color:#898887;'>-- The sequential multiplier will use \
this signal too, IF it takes 8 cycles.</span> +
+ready <span style='color:#006e28;'><=</span> <span \
style='color:#b08000;'>'1'</span> <b>when</b> bit_ctr <span \
style='color:#006e28;'>>=</span> <span style='color:#b08000;'>8</span> else <span \
style='color:#b08000;'>'0'</span>; +
+
+<span style='color:#898887;'>---- Divider logic \
-------------------------------------------------------------</span> +
+<span style='color:#898887;'>-- What we do is a simple base-2 'shift-and-subtract' \
algorithm that takes</span> +<span style='color:#898887;'>-- 8 cycles to complete. We \
can get away with this because we deal with unsigned</span> +<span \
style='color:#898887;'>-- numbers only.</span> +
+divider_registers<span style='color:#006e28;'>:</span>
+<b><span style='color:#0099aa;'>process</span></b>(clk)
+<b><span style='color:#0099aa;'>begin</span></b>
+ <b><span style='color:#223388;'>if</span></b> clk<span \
style='color:#b08000;'>'event</span> <b>and</b> clk<span \
style='color:#006e28;'>=</span><span style='color:#b08000;'>'1'</span> <b><span \
style='color:#223388;'>then</span></b> + <span style='color:#898887;'>-- \
denominator shift register</span> + <b><span \
style='color:#223388;'>if</span></b> load_regs<span \
style='color:#006e28;'>=</span><span style='color:#b08000;'>'1'</span> <b><span \
style='color:#223388;'>then</span></b> + b_shift_reg <span \
style='color:#006e28;'><=</span> <span style='color:#bf0303;'>"0"</span> \
<span style='color:#006e28;'>&</span> data_b <span \
style='color:#006e28;'>&</span> <span \
style='color:#bf0303;'>"0000000"</span>; + <span \
style='color:#898887;'>-- Division overflow can be determined upon loading B reg \
data.</span> + <span style='color:#898887;'>-- OV will be raised only on \
div-by-zero.</span> + <b><span style='color:#223388;'>if</span></b> \
data_b<span style='color:#006e28;'>=</span>X<span \
style='color:#bf0303;'>"00"</span> <b><span \
style='color:#223388;'>then</span></b> + div_ov_out <span \
style='color:#006e28;'><=</span> <span style='color:#b08000;'>'1'</span>; + \
<b><span style='color:#223388;'>else</span></b> + div_ov_out <span \
style='color:#006e28;'><=</span> <span style='color:#b08000;'>'0'</span>; + \
<b><span style='color:#223388;'>end if;</span></b> + <b><span \
style='color:#223388;'>else</span></b> + b_shift_reg <span \
style='color:#006e28;'><=</span> <span style='color:#bf0303;'>"0"</span> \
<span style='color:#006e28;'>&</span> b_shift_reg(b_shift_reg<span \
style='color:#b08000;'>'high</span> <span style='color:#006e28;'>downto</span> <span \
style='color:#b08000;'>1</span>); + <b><span style='color:#223388;'>end \
if;</span></b> +
+ <span style='color:#898887;'>-- numerator register</span>
+ <b><span style='color:#223388;'>if</span></b> load_regs<span \
style='color:#006e28;'>=</span><span style='color:#b08000;'>'1'</span> <b><span \
style='color:#223388;'>then</span></b> + rem_reg <span \
style='color:#006e28;'><=</span> data_a; + <b><span \
style='color:#223388;'>elsif</span></b> bit_ctr<span \
style='color:#006e28;'>/=</span><span style='color:#b08000;'>8</span> <b>and</b> \
sub_num<span style='color:#006e28;'>=</span><span style='color:#b08000;'>'1'</span> \
<b><span style='color:#223388;'>then</span></b> + rem_reg <span \
style='color:#006e28;'><=</span> rem_reg <span style='color:#006e28;'>-</span> \
denominator; + <b><span style='color:#223388;'>end if;</span></b>
+
+ <span style='color:#898887;'>--- quotient register</span>
+ <b><span style='color:#223388;'>if</span></b> load_regs<span \
style='color:#006e28;'>=</span><span style='color:#b08000;'>'1'</span> <b><span \
style='color:#223388;'>then</span></b> + quot_reg <span \
style='color:#006e28;'><=</span> (<span style='color:#006e28;'>others</span> <span \
style='color:#006e28;'>=></span> <span style='color:#b08000;'>'0'</span>); + \
<b><span style='color:#223388;'>elsif</span></b> bit_ctr<span \
style='color:#006e28;'>/=</span><span style='color:#b08000;'>8</span> <b><span \
style='color:#223388;'>then</span></b> + quot_reg <span \
style='color:#006e28;'><=</span> quot_reg(quot_reg<span \
style='color:#b08000;'>'high-1</span> <span style='color:#006e28;'>downto</span> \
<span style='color:#b08000;'>0</span>) <span style='color:#006e28;'>&</span> \
sub_num; + <b><span style='color:#223388;'>end if;</span></b>
+
+ load_regs <span style='color:#006e28;'><=</span> start;
+ <b><span style='color:#223388;'>end if;</span></b>
+<b><span style='color:#0099aa;'>end process </span></b>divider_registers;
+
+denominator <span style='color:#006e28;'><=</span> b_shift_reg(<span \
style='color:#b08000;'>7</span> <span style='color:#006e28;'>downto</span> <span \
style='color:#b08000;'>0</span>); +
+<span style='color:#898887;'>-- The 16-bit comparison between b_shift_reg \
(denominator) and the zero-extended </span> +<span style='color:#898887;'>-- rem_reg \
(numerator) can be simplified by splitting it in 2: </span> +<span \
style='color:#898887;'>-- If the shifted denominator high byte is not zero, it is \
>=256...</span> +den_ge_256 <span style='color:#006e28;'><=</span> <span \
style='color:#b08000;'>'1'</span> <b>when</b> b_shift_reg(<span \
style='color:#b08000;'>15</span> <span style='color:#006e28;'>downto</span> <span \
style='color:#b08000;'>8</span>) <span style='color:#006e28;'>/=</span> X<span \
style='color:#bf0303;'>"00"</span> else <span \
style='color:#b08000;'>'0'</span>; +<span style='color:#898887;'>-- ...otherwise we \
need to compare the low bytes.</span> +num_ge_den <span \
style='color:#006e28;'><=</span> <span style='color:#b08000;'>'1'</span> \
<b>when</b> rem_reg <span style='color:#006e28;'>>=</span> denominator else <span \
style='color:#b08000;'>'0'</span>; +sub_num <span style='color:#006e28;'><=</span> \
<span style='color:#b08000;'>'1'</span> <b>when</b> den_ge_256<span \
style='color:#006e28;'>=</span><span style='color:#b08000;'>'0'</span> <b>and</b> \
num_ge_den<span style='color:#006e28;'>=</span><span \
style='color:#b08000;'>'1'</span> else <span style='color:#b08000;'>'0'</span>; +
+
+quot_out <span style='color:#006e28;'><=</span> quot_reg;
+prod_out <span style='color:#006e28;'><=</span> prod_reg;
+rem_out <span style='color:#006e28;'><=</span> rem_reg;
+
+div_ready <span style='color:#006e28;'><=</span> ready;
+
+<span style='color:#898887;'>---- Multiplier logic \
----------------------------------------------------------</span> +
+<span style='color:#898887;'>---- Combinational multiplier \
-----------------------------</span> +multiplier_combinational<span \
style='color:#006e28;'>:</span> +if <b>not</b> SEQUENTIAL_MULTIPLIER <b>generate</b>
+
+registered_combinational_multiplier<span style='color:#006e28;'>:</span>
+<b><span style='color:#0099aa;'>process</span></b>(clk)
+<b><span style='color:#0099aa;'>begin</span></b>
+ <b><span style='color:#223388;'>if</span></b> clk<span \
style='color:#b08000;'>'event</span> <b>and</b> clk<span \
style='color:#006e28;'>=</span><span style='color:#b08000;'>'1'</span> <b><span \
style='color:#223388;'>then</span></b> + prod_reg <span \
style='color:#006e28;'><=</span> data_a <span style='color:#006e28;'>*</span> \
data_b; <span style='color:#898887;'>-- t_byte is unsigned</span> + <b><span \
style='color:#223388;'>end if;</span></b> +<b><span style='color:#0099aa;'>end \
process </span></b>registered_combinational_multiplier; +
+<span style='color:#898887;'>-- The multiplier output is valid in the cycle after \
the operands are loaded,</span> +<span style='color:#898887;'>-- so by the time MUL \
is executed it's already done.</span> +mul_ready <span \
style='color:#006e28;'><=</span> <span style='color:#b08000;'>'1'</span>; +
+mul_ov_out <span style='color:#006e28;'><=</span> <span \
style='color:#b08000;'>'1'</span> <b>when</b> prod_reg(<span \
style='color:#b08000;'>15</span> <span style='color:#006e28;'>downto</span> <span \
style='color:#b08000;'>8</span>)<span style='color:#006e28;'>/=</span>X<span \
style='color:#bf0303;'>"00"</span> else <span \
style='color:#b08000;'>'0'</span>; +prod_out <span \
style='color:#006e28;'><=</span> prod_reg; +
+<b>end</b> <b>generate</b> multiplier_combinational;
+
+<span style='color:#898887;'>---- Sequential multiplier \
--------------------------------</span> +multiplier_sequential<span \
style='color:#006e28;'>:</span> +if SEQUENTIAL_MULTIPLIER <b>generate</b>
+
+<b>assert</b> false
+<b>report</b> <span style='color:#bf0303;'>"Sequential multiplier \
implementation not done yet."</span><span style='color:#006e28;'>&</span> + \
<span style='color:#bf0303;'>" Use combinational implementation."</span> \
+<b>severity</b> <b>failure</b>; +
+<b>end</b> <b>generate</b> multiplier_sequential;
+
+<b><span style='color:#223388;'>end sequential;</span></b>
+</pre>
+</body>
+</html>
diff --git a/autotests/input/syntax/vhdl/results/light52_tb.vhdl.reference.html \
b/autotests/input/syntax/vhdl/results/light52_tb.vhdl.reference.html new file mode \
100644 index 0000000..b10b1d3
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@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "DTD/xhtml1-strict.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
+<meta name="Generator" content="Kate, the KDE Advanced Text Editor" />
+<title>light52_tb.vhdl</title>
+</head>
+<body>
+<pre style='color:#1f1c1b;background-color:#ffffff;'>
+<span style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- light52_tb.vhdl -- </span>
+<span style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- This test bench simulates the execution of some \
program (whose object code</span> +<span style='color:#898887;'>-- is in package \
obj_code_pkg, in the form of a memory init constant) and logs</span> +<span \
style='color:#898887;'>-- the execution to a text file called 'hw_sim_log.txt' \
(light52_tb_pkg.vhdl).</span> +<span style='color:#898887;'>--</span>
+<span style='color:#898887;'>-- This test bench does no actual tests on the core. \
Instead, the simulation log</span> +<span style='color:#898887;'>-- is meant to be \
matched against the simulation log produced by running the </span> +<span \
style='color:#898887;'>-- same program on the software simulator B51 (also included \
with this project).</span> +<span style='color:#898887;'>-- </span>
+<span style='color:#898887;'>-- This will catch errors in the implementation of the \
CPU if the simulated</span> +<span style='color:#898887;'>-- program has anough \
coverage -- the opcode tester is meant to cover all CPU</span> +<span \
style='color:#898887;'>-- opcodes in many (not all) of their corner cases.</span> \
+<span style='color:#898887;'>-- This scheme will not help in catching errors in the \
peripheral modules, </span> +<span style='color:#898887;'>-- mainly because the \
current version of B51 does not simulate them.</span> +<span \
style='color:#898887;'>--</span> +<span \
style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- Copyright (C) 2012 Jose A. Ruiz</span>
+<span style='color:#898887;'>-- \
</span> +<span style='color:#898887;'>-- This source file may be used and distributed \
without </span> +<span style='color:#898887;'>-- restriction provided that \
this copyright statement is not </span> +<span style='color:#898887;'>-- removed \
from the file and that any derivative work contains </span> +<span \
style='color:#898887;'>-- the original copyright notice and the associated \
disclaimer. </span> +<span style='color:#898887;'>-- \
</span> +<span style='color:#898887;'>-- This source file is free software; you can \
redistribute it </span> +<span style='color:#898887;'>-- and/or modify it under the \
terms of the GNU Lesser General </span> +<span style='color:#898887;'>-- Public \
License as published by the Free Software Foundation; </span> +<span \
style='color:#898887;'>-- either version 2.1 of the License, or (at your option) any \
</span> +<span style='color:#898887;'>-- later version. \
</span> +<span style='color:#898887;'>-- \
</span> +<span style='color:#898887;'>-- This source is distributed in the hope that \
it will be </span> +<span style='color:#898887;'>-- useful, but WITHOUT ANY \
WARRANTY; without even the implied </span> +<span style='color:#898887;'>-- \
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR </span> +<span \
style='color:#898887;'>-- PURPOSE. See the GNU Lesser General Public License for \
more </span> +<span style='color:#898887;'>-- details. \
</span> +<span style='color:#898887;'>-- \
</span> +<span style='color:#898887;'>-- You should have received a copy of the GNU \
Lesser General </span> +<span style='color:#898887;'>-- Public License along with \
this source; if not, download it </span> +<span style='color:#898887;'>-- from \
http://www.opencores.org/lgpl.shtml</span> +<span \
style='color:#898887;'>--------------------------------------------------------------------------------</span>
+
+
+<b>library</b> ieee;
+<b>use</b> ieee<span style='color:#006e28;'>.</span>std_logic_1164<span \
style='color:#006e28;'>.</span>all; +<b>use</b> ieee<span \
style='color:#006e28;'>.</span>std_logic_arith<span \
style='color:#006e28;'>.</span>all; +<b>use</b> ieee<span \
style='color:#006e28;'>.</span>std_logic_unsigned<span \
style='color:#006e28;'>.</span>all; +<b>use</b> std<span \
style='color:#006e28;'>.</span>textio<span style='color:#006e28;'>.</span>all; +
+<b>use</b> work<span style='color:#006e28;'>.</span>light52_pkg<span \
style='color:#006e28;'>.</span>all; +<b>use</b> work<span \
style='color:#006e28;'>.</span>obj_code_pkg<span style='color:#006e28;'>.</span>all; \
+<b>use</b> work<span style='color:#006e28;'>.</span>light52_tb_pkg<span \
style='color:#006e28;'>.</span>all; +<b>use</b> work<span \
style='color:#006e28;'>.</span>txt_util<span style='color:#006e28;'>.</span>all; +
+<b><span style='color:#223388;'>entity</span></b> <b><span \
style='color:#bb6600;'>light52_tb</span></b> <b>is</b> +<b><span \
style='color:#223388;'>generic</span></b> (BCD <span style='color:#006e28;'>:</span> \
<span style='color:#0057ae;'>boolean</span> <span style='color:#006e28;'>:=</span> \
true); +<b><span style='color:#223388;'>end;</span></b>
+
+
+<b><span style='color:#223388;'>architecture</span></b> <b><span \
style='color:#bb6600;'>testbench</span></b> <b>of</b> <span \
style='color:#644a9b;'>light52_tb</span> <b>is</b> +
+<span style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- Simulation parameters</span>
+<span style='color:#898887;'>-- FIXME these should be in parameter package</span>
+
+<span style='color:#898887;'>-- Simulated clock period is the same as the usual \
target, the DE-1 board</span> +<span style='color:#006e28;'>constant</span> T <span \
style='color:#006e28;'>:</span> <span style='color:#0057ae;'>time</span> <span \
style='color:#006e28;'>:=</span> <span style='color:#b08000;'>20</span> <span \
style='color:#0057ae;'>ns</span>; <span style='color:#898887;'>-- 50MHz</span> +<span \
style='color:#006e28;'>constant</span> SIMULATION_LENGTH <span \
style='color:#006e28;'>:</span> <span style='color:#0057ae;'>integer</span> <span \
style='color:#006e28;'>:=</span> <span style='color:#b08000;'>400000</span>; +
+<span style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- MPU interface </span>
+
+<span style='color:#006e28;'>signal</span> clk <span style='color:#006e28;'>:</span> \
<span style='color:#0057ae;'>std_logic</span> <span style='color:#006e28;'>:=</span> \
<span style='color:#b08000;'>'0'</span>; +<span style='color:#006e28;'>signal</span> \
reset <span style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic</span> <span style='color:#006e28;'>:=</span> <span \
style='color:#b08000;'>'1'</span>; +
+<span style='color:#006e28;'>signal</span> p0_out <span \
style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic_vector</span>(<span style='color:#b08000;'>7</span> \
<span style='color:#006e28;'>downto</span> <span style='color:#b08000;'>0</span>); \
+<span style='color:#006e28;'>signal</span> p1_out <span \
style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic_vector</span>(<span style='color:#b08000;'>7</span> \
<span style='color:#006e28;'>downto</span> <span style='color:#b08000;'>0</span>); \
+<span style='color:#006e28;'>signal</span> p2_in <span \
style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic_vector</span>(<span style='color:#b08000;'>7</span> \
<span style='color:#006e28;'>downto</span> <span style='color:#b08000;'>0</span>); \
+<span style='color:#006e28;'>signal</span> p3_in <span \
style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic_vector</span>(<span style='color:#b08000;'>7</span> \
<span style='color:#006e28;'>downto</span> <span style='color:#b08000;'>0</span>); +
+<span style='color:#006e28;'>signal</span> external_irq <span \
style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic_vector</span>(<span style='color:#b08000;'>7</span> \
<span style='color:#006e28;'>downto</span> <span style='color:#b08000;'>0</span>); +
+<span style='color:#006e28;'>signal</span> txd<span style='color:#006e28;'>,</span> \
rxd <span style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic</span>; +
+<span style='color:#898887;'>--------------------------------------------------------------------------------</span>
+<span style='color:#898887;'>-- Logging signals & simulation control </span>
+
+<span style='color:#898887;'>-- Asserted high to disable the clock and terminate the \
simulation.</span> +<span style='color:#006e28;'>signal</span> done <span \
style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>std_logic</span> <span style='color:#006e28;'>:=</span> <span \
style='color:#b08000;'>'0'</span>; +
+<span style='color:#898887;'>-- Log file</span>
+<b>file</b> log_file<span style='color:#006e28;'>:</span> <span \
style='color:#0057ae;'>TEXT</span> <b>open</b> write_mode <b>is</b> <span \
style='color:#bf0303;'>"hw_sim_log.txt"</span>; +<span \
style='color:#898887;'>-- Console output log file</span> +<b>file</b> con_file<span \
style='color:#006e28;'>:</span> <span style='color:#0057ae;'>TEXT</span> <b>open</b> \
write_mode <b>is</b> <span \
style='color:#bf0303;'>"hw_sim_console_log.txt"</span>; +<span \
style='color:#898887;'>-- Info record needed by the logging fuctions</span> +<span \
style='color:#006e28;'>signal</span> log_info <span style='color:#006e28;'>:</span> \
t_log_info; +
+<b><span style='color:#223388;'>begin</span></b>
+
+<span style='color:#898887;'>---- UUT instantiation \
---------------------------------------------------------</span> +
+<b><span style='color:#bb6600;'>uut</span></b><span style='color:#006e28;'>:</span> \
<span style='color:#644a9b;'>entity work.light52_mcu</span> + <b>generic map (</b>
+ IMPLEMENT_BCD_INSTRUCTIONS <span style='color:#006e28;'>=></span> \
BCD<span style='color:#006e28;'>,</span> + CODE_ROM_SIZE <span \
style='color:#006e28;'>=></span> work<span \
style='color:#006e28;'>.</span>obj_code_pkg<span \
style='color:#006e28;'>.</span>XCODE_SIZE<span style='color:#006e28;'>,</span> + \
XDATA_RAM_SIZE <span style='color:#006e28;'>=></span> work<span \
style='color:#006e28;'>.</span>obj_code_pkg<span \
style='color:#006e28;'>.</span>XDATA_SIZE<span style='color:#006e28;'>,</span> + \
OBJ_CODE <span style='color:#006e28;'>=></span> work<span \
style='color:#006e28;'>.</span>obj_code_pkg<span \
style='color:#006e28;'>.</span>object_code + )
+ <b>port map (</b>
+ clk <span style='color:#006e28;'>=></span> clk<span \
style='color:#006e28;'>,</span> + reset <span \
style='color:#006e28;'>=></span> reset<span style='color:#006e28;'>,</span> + \
+ txd <span style='color:#006e28;'>=></span> txd<span \
style='color:#006e28;'>,</span> + rxd <span \
style='color:#006e28;'>=></span> rxd<span style='color:#006e28;'>,</span> + \
+ external_irq <span style='color:#006e28;'>=></span> external_irq<span \
style='color:#006e28;'>,</span> +
+ p0_out <span style='color:#006e28;'>=></span> p0_out<span \
style='color:#006e28;'>,</span> + p1_out <span \
style='color:#006e28;'>=></span> p1_out<span style='color:#006e28;'>,</span> + \
p2_in <span style='color:#006e28;'>=></span> p2_in<span \
style='color:#006e28;'>,</span> + p3_in <span \
style='color:#006e28;'>=></span> p3_in + );
+
+ <span style='color:#898887;'>-- UART is looped back in the test bench.</span>
+ rxd <span style='color:#006e28;'><=</span> txd;
+
+ <span style='color:#898887;'>-- I/O ports are looped back and otherwise \
unused.</span> + p2_in <span style='color:#006e28;'><=</span> p0_out;
+ p3_in <span style='color:#006e28;'><=</span> p1_out;
+
+ <span style='color:#898887;'>-- External IRQ inputs are tied to port P1 for test \
purposes</span> + external_irq <span style='color:#006e28;'><=</span> p1_out;
+
+ <span style='color:#898887;'>---- Master clock: free running clock used as main \
module clock ------------</span> + run_master_clock<span \
style='color:#006e28;'>:</span> + <b><span \
style='color:#0099aa;'>process</span></b>(done<span style='color:#006e28;'>,</span> \
clk) + <b><span style='color:#0099aa;'>begin</span></b>
+ <b><span style='color:#223388;'>if</span></b> done <span \
style='color:#006e28;'>=</span> <span style='color:#b08000;'>'0'</span> <b><span \
style='color:#223388;'>then</span></b> + clk <span \
style='color:#006e28;'><=</span> <b>not</b> clk <b>after</b> T<span \
style='color:#006e28;'>/</span><span style='color:#b08000;'>2</span>; + \
<b><span style='color:#223388;'>end if;</span></b> + <b><span \
style='color:#0099aa;'>end process </span></b>run_master_clock; +
+
+ <span style='color:#898887;'>---- Main simulation process: reset MCU and wait \
for fixed period ----------</span> +
+ drive_uut<span style='color:#006e28;'>:</span>
+ <b><span style='color:#0099aa;'>process</span></b>
+ <b><span style='color:#0099aa;'>begin</span></b>
+ <span style='color:#898887;'>-- Leave reset asserted for a few clock \
cycles...</span> + reset <span style='color:#006e28;'><=</span> <span \
style='color:#b08000;'>'1'</span>; + <b>wait</b> for T<span \
style='color:#006e28;'>*</span><span style='color:#b08000;'>4</span>; + reset \
<span style='color:#006e28;'><=</span> <span style='color:#b08000;'>'0'</span>; + \
+ <span style='color:#898887;'>-- ...and wait for the test to hit a \
termination condition (evaluated by</span> + <span style='color:#898887;'>-- \
function log_cpu_activity) or to just timeout.</span> + <b>wait</b> for T<span \
style='color:#006e28;'>*</span>SIMULATION_LENGTH; +
+ <span style='color:#898887;'>-- If we arrive here, the simulation timed out \
(termination conditions</span> + <span style='color:#898887;'>-- trigger a \
failed assertion).</span> + <span style='color:#898887;'>-- So print a timeout \
message and quit.</span> + print(<span style='color:#bf0303;'>"TB timed \
out."</span>); + done <span style='color:#006e28;'><=</span> <span \
style='color:#b08000;'>'1'</span>; + <b>wait</b>;
+
+ <b><span style='color:#0099aa;'>end process </span></b>drive_uut;
+
+
+ <span style='color:#898887;'>-- Logging process: launch logger functions \
--------------------------------</span> + log_execution<span \
style='color:#006e28;'>:</span> + <b><span \
style='color:#0099aa;'>process</span></b> + <b><span \
style='color:#0099aa;'>begin</span></b> + <span style='color:#898887;'>-- Log \
cpu activity until done='1'.</span> + log_cpu_activity(clk<span \
style='color:#006e28;'>,</span> reset<span style='color:#006e28;'>,</span> done<span \
style='color:#006e28;'>,</span> <span \
style='color:#bf0303;'>"/uut"</span><span style='color:#006e28;'>,</span> + \
log_info<span style='color:#006e28;'>,</span> work<span \
style='color:#006e28;'>.</span>obj_code_pkg<span \
style='color:#006e28;'>.</span>XCODE_SIZE<span style='color:#006e28;'>,</span> <span \
style='color:#bf0303;'>"log_info"</span><span \
style='color:#006e28;'>,</span> + X<span \
style='color:#bf0303;'>"0000"</span><span style='color:#006e28;'>,</span> \
log_file<span style='color:#006e28;'>,</span> con_file); +
+ <span style='color:#898887;'>-- Flush console log file when finished.</span>
+ log_flush_console(log_info<span style='color:#006e28;'>,</span> con_file);
+
+ <b>wait</b>;
+ <b><span style='color:#0099aa;'>end process </span></b>log_execution;
+
+<b><span style='color:#223388;'>end architecture testbench;</span></b>
+</pre>
+</body>
+</html>
diff --git a/autotests/src/katesyntaxtest.cpp b/autotests/src/katesyntaxtest.cpp
new file mode 100644
index 0000000..c99a5c6
--- /dev/null
+++ b/autotests/src/katesyntaxtest.cpp
@@ -0,0 +1,129 @@
+/* This file is part of the Kate project.
+ *
+ * Copyright (C) 2013 Dominik Haumann <dhaumann@kde.org>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public License
+ * along with this library; see the file COPYING.LIB. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include "katesyntaxtest.h"
+
+#include <kateglobal.h>
+#include <katebuffer.h>
+#include <katedocument.h>
+#include <kateview.h>
+#include <kateconfig.h>
+#include <katetextfolding.h>
+
+#include <QtTestWidgets>
+#include <QDirIterator>
+#include <QFileInfo>
+#include <QProcess>
+
+QTEST_MAIN(KateSyntaxTest)
+
+void KateSyntaxTest::initTestCase()
+{
+}
+
+void KateSyntaxTest::cleanupTestCase()
+{
+}
+
+void KateSyntaxTest::testSyntaxHighlighting_data()
+{
+ QTest::addColumn<QString>("hlTestCase");
+
+ /**
+ * check for directories, one dir == one hl
+ */
+ const QString testDir(QLatin1String(TEST_DATA_DIR) + QLatin1String("/syntax/"));
+ QDirIterator contents(testDir);
+ while (contents.hasNext()) {
+ const QString hlDir = contents.next();
+ const QFileInfo info(hlDir);
+ if (!info.isDir() || hlDir.contains(QLatin1Char('.'))) {
+ continue;
+ }
+
+ /**
+ * now: get the tests per hl
+ */
+ QDirIterator contents(hlDir);
+ while (contents.hasNext()) {
+ const QString hlTestCase = contents.next();
+ const QFileInfo info(hlTestCase);
+ if (!info.isFile()) {
+ continue;
+ }
+
+ QTest::newRow(info.absoluteFilePath().toLocal8Bit().constData()) << \
info.absoluteFilePath(); + }
+ }
+}
+
+
+void KateSyntaxTest::testSyntaxHighlighting()
+{
+ /**
+ * get current test case
+ */
+ QFETCH(QString, hlTestCase);
+
+ qDebug() << hlTestCase;
+
+ /**
+ * create a document with a view to be able to export stuff
+ */
+ KTextEditor::DocumentPrivate doc;
+ auto view = static_cast<KTextEditor::ViewPrivate*>(doc.createView(Q_NULLPTR));
+
+ /**
+ * load the test case
+ */
+ QUrl url;
+ url.setScheme(QLatin1String("file"));
+ url.setPath(hlTestCase);
+ QVERIFY(doc.openUrl(url));
+
+ /**
+ * compute needed dirs
+ */
+ const QFileInfo info(hlTestCase);
+ const QString resultDir(info.absolutePath() + QLatin1String("/results/"));
+ const QString currentResult(resultDir + info.fileName() + \
QLatin1String(".current.html")); + const QString referenceResult(resultDir + \
info.fileName() + QLatin1String(".reference.html")); +
+ /**
+ * export the result
+ */
+ view->exportHtmlToFile(currentResult);
+
+ /**
+ * verify the result against reference
+ */
+ QProcess diff;
+ QStringList args;
+ args << QLatin1String("-u") << (referenceResult) << (currentResult);
+ diff.start(QLatin1String("diff"), args);
+ diff.waitForFinished();
+ QByteArray out = diff.readAllStandardOutput();
+ QByteArray err = diff.readAllStandardError();
+ if (!err.isEmpty()) {
+ qWarning() << err;
+ }
+ QCOMPARE(QString::fromLocal8Bit(out), QString());
+ QCOMPARE(diff.exitCode(), EXIT_SUCCESS);
+}
diff --git a/autotests/src/katesyntaxtest.h b/autotests/src/katesyntaxtest.h
new file mode 100644
index 0000000..5c105a0
--- /dev/null
+++ b/autotests/src/katesyntaxtest.h
@@ -0,0 +1,38 @@
+/* This file is part of the KDE libraries
+ Copyright (C) 2013 Dominik Haumann <dhaumann@kde.org>
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Library General Public
+ License as published by the Free Software Foundation; either
+ version 2 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Library General Public License for more details.
+
+ You should have received a copy of the GNU Library General Public License
+ along with this library; see the file COPYING.LIB. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+*/
+
+#ifndef KATE_SYNTAX_TEST_H
+#define KATE_SYNTAX_TEST_H
+
+#include <QtCore/QObject>
+
+class KateSyntaxTest : public QObject
+{
+ Q_OBJECT
+
+public Q_SLOTS:
+ void initTestCase();
+ void cleanupTestCase();
+
+private Q_SLOTS:
+ void testSyntaxHighlighting_data();
+ void testSyntaxHighlighting();
+};
+
+#endif // KATE_FOLDING_TEST_H
diff --git a/src/export/exporter.cpp b/src/export/exporter.cpp
index ac32b5a..eaedb4a 100644
--- a/src/export/exporter.cpp
+++ b/src/export/exporter.cpp
@@ -56,20 +56,13 @@ void KateExporter::exportToClipboard()
QApplication::clipboard()->setMimeData(data);
}
-void KateExporter::exportToFile()
+void KateExporter::exportToFile(const QString &file)
{
- //FIXME KF5, crashy
-
- QString fileName = QFileDialog::getSaveFileName(m_view, i18n("Export File as \
HTML"), m_view->document()->documentName());
- if (fileName.isEmpty()) {
- return;
- }
-
- QSaveFile savefile(fileName);
+ QFile savefile(file);
if (!savefile.open(QIODevice::WriteOnly | QIODevice::Truncate)) {
return;
}
-
+
QTextStream outputStream(&savefile);
exportData(false, outputStream);
}
@@ -83,7 +76,6 @@ void KateExporter::exportData(const bool useSelection, QTextStream \
&output) return;
}
- //outputStream.setEncoding(QTextStream::UnicodeUTF8);
output.setCodec(QTextCodec::codecForName("UTF-8"));
///TODO: add more exporters
diff --git a/src/export/exporter.h b/src/export/exporter.h
index 29eaf76..ec931a2 100644
--- a/src/export/exporter.h
+++ b/src/export/exporter.h
@@ -33,7 +33,7 @@ public:
}
void exportToClipboard();
- void exportToFile();
+ void exportToFile(const QString &file);
private:
///TODO: maybe make this scriptable for additional exporters?
diff --git a/src/view/kateview.cpp b/src/view/kateview.cpp
index 5faec88..56f3e95 100644
--- a/src/view/kateview.cpp
+++ b/src/view/kateview.cpp
@@ -3174,14 +3174,22 @@ void KTextEditor::ViewPrivate::applyFoldingState()
m_savedFoldingState.clear();
}
+void KTextEditor::ViewPrivate::exportHtmlToFile(const QString &file)
+{
+ KateExporter(this).exportToFile(file);
+}
+
void KTextEditor::ViewPrivate::exportHtmlToClipboard ()
{
- KateExporter (this).exportToClipboard ();
+ KateExporter(this).exportToClipboard();
}
void KTextEditor::ViewPrivate::exportHtmlToFile ()
{
- KateExporter (this).exportToFile ();
+ const QString file = QFileDialog::getSaveFileName(this, i18n("Export File as \
HTML"), m_doc->documentName()); + if (!file.isEmpty()) {
+ KateExporter(this).exportToFile(file);
+ }
}
void KTextEditor::ViewPrivate::clearHighlights()
diff --git a/src/view/kateview.h b/src/view/kateview.h
index d972c03..624072e 100644
--- a/src/view/kateview.h
+++ b/src/view/kateview.h
@@ -584,6 +584,8 @@ public:
public:
void slotTextInserted(KTextEditor::View *view, const KTextEditor::Cursor \
&position, const QString &text); +
+ void exportHtmlToFile(const QString &file);
private Q_SLOTS:
void slotGotFocus();
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