[prev in list] [next in list] [prev in thread] [next in thread] 

List:       usrp-users
Subject:    Re: [USRP-users] Creating custom image ends mostly in timing problems inside ettus blocks (X310)
From:       Jonathon Pendlum via USRP-users <usrp-users () lists ! ettus ! com>
Date:       2016-05-30 2:46:05
Message-ID: CAGdo0uQYp0a5L9PtmRGxBC=SuKffNvfY+EtGAgYrVw1XUYx+Lg () mail ! gmail ! com
[Download RAW message or body]

[Attachment #2 (multipart/alternative)]


Hi Patrick,

What device are targeting? What clock rate did you use for timing? Are you
working off master or maint? How and where is your design inserted in the
radio.v processing chain?



Jonathon

On Thu, May 26, 2016 at 3:02 PM, Patrick Berger via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi every body
>
> I've created a custom block in xilinx system generator for a psd
> estimation with an iir filter. Inside system generator I can create a
> timing analysis (post route) without any problems (worst negativ slack is
> ~3ns).
> When I create an IP core and add the core to the default Vivado project
> inside the radio.v module and try to synthezise the design I get in 90%
> timing problems with the rgpio module (rgpio_atr and the radio_clk signal).
> The number failing endpoints are about 1 to 15. Chanching the
> implementation and synthesis strategie improves the design, but it fails
> the timing check.
>
> How could that be? My psd modul needs about 1-3% from the fpga ressources,
> so it isn't so big. the output bus is only 50 bits width.
>
> Does anyone have some experience with sutch problems?
>
> Best regards
> Patrick
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>

[Attachment #5 (text/html)]

<div dir="ltr">Hi Patrick,<div><br></div><div>What device are targeting? What clock \
rate did you use for timing? Are you working off master or maint? How and where is \
your design inserted in the radio.v processing \
chain?</div><div><br></div><div><br></div><div><br></div><div>Jonathon</div></div><div \
class="gmail_extra"><br><div class="gmail_quote">On Thu, May 26, 2016 at 3:02 PM, \
Patrick Berger via USRP-users <span dir="ltr">&lt;<a \
href="mailto:usrp-users@lists.ettus.com" \
target="_blank">usrp-users@lists.ettus.com</a>&gt;</span> wrote:<br><blockquote \
class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc \
solid;padding-left:1ex">


<div><div dir="ltr">Hi every body<br><br>I&#39;ve created a custom block in xilinx \
system generator for a psd estimation with an iir filter. Inside system generator I \
can create a timing analysis (post route) without any problems (worst negativ slack \
is ~3ns).<br>When I create an IP core and add the core to the default Vivado project \
inside the radio.v module and try to synthezise the design I get in 90% timing \
problems with the rgpio module (rgpio_atr and the radio_clk signal). The number \
failing endpoints are about 1 to 15. Chanching the implementation and synthesis \
strategie improves the design, but it fails the timing check.<br><br>How could that \
be? My psd modul needs about 1-3% from the fpga ressources, so it isn&#39;t so big. \
the output bus is only 50 bits width.<br><br>Does anyone have some experience with \
sutch problems?<br><br>Best regards<span class="HOEnZb"><font \
color="#888888"><br>Patrick <br> 		 	   		  </font></span></div></div> \
<br>_______________________________________________<br> USRP-users mailing list<br>
<a href="mailto:USRP-users@lists.ettus.com">USRP-users@lists.ettus.com</a><br>
<a href="http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com" \
rel="noreferrer" target="_blank">http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com</a><br>
 <br></blockquote></div><br></div>



_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com


[prev in list] [next in list] [prev in thread] [next in thread]