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List:       qemu-riscv
Subject:    Re: [PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled
From:       Daniel Henrique Barboza <dbarboza () ventanamicro ! com>
Date:       2023-05-30 20:26:21
Message-ID: c746c2a9-ef7b-4348-3567-4eb514f9dacb () ventanamicro ! com
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On 5/29/23 09:17, Weiwei Li wrote:
> MPV and GVA bits are added by hypervisor extension to mstatus
> and mstatush (if MXLEN=32).
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/csr.c | 10 ++++------
>   1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 58499b5afc..6ac11d1f11 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1311,11 +1311,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
>       }
>   
>       if (xl != MXL_RV32 || env->debugger) {
> -        /*
> -         * RV32: MPV and GVA are not in mstatus. The current plan is to
> -         * add them to mstatush. For now, we just don't support it.
> -         */
> -        mask |= MSTATUS_MPV | MSTATUS_GVA;
> +        if (riscv_has_ext(env, RVH)) {
> +            mask |= MSTATUS_MPV | MSTATUS_GVA;
> +        }
>           if ((val & MSTATUS64_UXL) != 0) {
>               mask |= MSTATUS64_UXL;
>           }
> @@ -1351,7 +1349,7 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
>                                        target_ulong val)
>   {
>       uint64_t valh = (uint64_t)val << 32;
> -    uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
> +    uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0;
>   
>       env->mstatus = (env->mstatus & ~mask) | (valh & mask);
>   

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