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List:       qemu-riscv
Subject:    Re: [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions
From:       Richard Henderson <richard.henderson () linaro ! org>
Date:       2020-07-30 20:47:13
Message-ID: 2498a5e8-4026-69e4-f402-8d1e85ef6dd1 () linaro ! org
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On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/insn_trans/trans_rvv.inc.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


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