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List:       qemu-riscv
Subject:    Re: [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions
From:       Richard Henderson <richard.henderson () linaro ! org>
Date:       2020-07-30 20:45:52
Message-ID: 5638f6d3-860d-d543-9498-b63f1ac8e7db () linaro ! org
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On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> Add the following instructions:
> 
> * vaaddu.vv
> * vaaddu.vx
> * vasubu.vv
> * vasubu.vx
> 
> Remove the following instructions:
> 
> * vadd.vi
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/helper.h                   | 16 ++++++
>  target/riscv/insn32.decode              | 13 +++--
>  target/riscv/insn_trans/trans_rvv.inc.c |  5 +-
>  target/riscv/vector_helper.c            | 74 +++++++++++++++++++++++++
>  4 files changed, 102 insertions(+), 6 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

> +static inline uint64_t aaddu64(CPURISCVState *env, int vxrm,
> +                               uint64_t a, uint64_t b)
> +{
> +    uint64_t res = a + b;
> +    uint8_t round = get_round(vxrm, res, 1);
> +    uint64_t over = res < a ? ((uint64_t)1 << 63) : 0;

You know you can write this as

    (uint64_t)(res < a) << 63

right?

r~


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