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List:       linux-arm-kernel
Subject:    patch for vector stubs
From:       Philip Blundell <philb () gnu ! org>
Date:       2001-12-28 15:37:17
[Download RAW message or body]

This is against 2.4.16.  It's not necessary to load R13 anew each time an
exception happens; you can just initialise it once and then leave it alone.

p.

--- entry-armv.S	Sun Dec  2 13:45:08 2001
+++ entry-armv.S	Fri Dec 28 11:51:19 2001
@@ -875,7 +875,6 @@
 vector_IRQ:	@
 		@ save mode specific registers
 		@
-		ldr	r13, .LCsirq
 		sub	lr, lr, #4
 		str	lr, [r13]			@ save lr_IRQ
 		mrs	lr, spsr
@@ -883,8 +882,7 @@
 		@
 		@ now branch to the relevent MODE handling routine
 		@
-		mov	r13, #I_BIT | MODE_SVC
-		msr	spsr_c, r13			@ switch to SVC_32 mode
+		msr	spsr_c, #I_BIT | MODE_SVC	@ switch to SVC_32 mode
 
 		and	lr, lr, #15
 		ldr	lr, [pc, lr, lsl #2]
@@ -916,7 +914,6 @@
 vector_data:	@
 		@ save mode specific registers
 		@
-		ldr	r13, .LCsabt
 		sub	lr, lr, #8
 		str	lr, [r13]
 		mrs	lr, spsr
@@ -924,8 +921,7 @@
 		@
 		@ now branch to the relevent MODE handling routine
 		@
-		mov	r13, #I_BIT | MODE_SVC
-		msr	spsr_c, r13			@ switch to SVC_32 mode
+		msr	spsr_c, #I_BIT | MODE_SVC	@ switch to SVC_32 mode
 
 		and	lr, lr, #15
 		ldr	lr, [pc, lr, lsl #2]
@@ -958,7 +954,6 @@
 		@
 		@ save mode specific registers
 		@
-		ldr	r13, .LCsabt
 		sub	lr, lr, #4
 		str	lr, [r13]			@ save lr_ABT
 		mrs	lr, spsr
@@ -966,8 +961,7 @@
 		@
 		@ now branch to the relevent MODE handling routine
 		@
-		mov	r13, #I_BIT | MODE_SVC
-		msr	spsr_c, r13			@ switch to SVC_32 mode
+		msr	spsr_c, #I_BIT | MODE_SVC	@ switch to SVC_32 mode
 
 		ands	lr, lr, #15
 		ldr	lr, [pc, lr, lsl #2]
@@ -1000,15 +994,13 @@
 		@
 		@ save mode specific registers
 		@
-		ldr	r13, .LCsund
 		str	lr, [r13]			@ save lr_UND
 		mrs	lr, spsr
 		str	lr, [r13, #4]			@ save spsr_UND
 		@
 		@ now branch to the relevent MODE handling routine
 		@
-		mov	r13, #I_BIT | MODE_SVC
-		msr	spsr_c, r13			@ switch to SVC_32 mode
+		msr	spsr_c, #I_BIT | MODE_SVC	@ switch to SVC_32 mode
 
 		and	lr, lr, #15
 		ldr	lr, [pc, lr, lsl #2]
@@ -1064,10 +1056,6 @@
 
 .LCvswi:	.word	vector_swi
 
-.LCsirq:	.word	__temp_irq
-.LCsund:	.word	__temp_und
-.LCsabt:	.word	__temp_abt
-
 __stubs_end:
 
 		.equ	__real_stubs_start, .LCvectors + 0x200
@@ -1095,6 +1083,16 @@
 		str	r3, [r2], #4
 		cmp	r0, r1
 		blt	1b
+
+		mrs	r0, cpsr
+		msr	cpsr, #ABT_MODE | I_BIT
+		ldr	r13, =__temp_abt
+		msr	cpsr, #UND_MODE | I_BIT
+		ldr	r13, =__temp_und
+		msr	cpsr, #IRQ_MODE | I_BIT
+		ldr	r13, =__temp_irq
+		msr	cpsr, r0
+	
 		LOADREGS(fd, sp!, {r4 - r6, pc})
 
 		.data



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