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List: kwrite-devel
Subject: Highlight xml file for VHDL@kate
From: Frederico de Faria -LME <ffaria () LME ! usp ! br>
Date: 2007-06-28 1:45:32
Message-ID: 468312BC.40306 () LME ! usp ! br
[Download RAW message or body]
Hi,
I've just made some changes on the 1.04 vhdl highlight file. As a hw
eng, I think the attached version is more complete.
Hope you take a look and upload this new version to the server.
Thanks.
Frederico.
ps: i'm not on this list, pls cc' me if any comments.
--
["vhdl.xml.2007-06-27-Qua-205455" (text/xml)]
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE language SYSTEM "language.dtd">
<language name="VHDL" version="1.05" kateversion="2.1" section="Hardware" \
extensions="*.vhdl;*.vhd" mimetype="text/x-vhdl"> <highlighting>
<list name="declaration">
<item> entity </item>
<item> map </item>
<item> architecture </item>
<item> array </item>
<item> attribute </item>
<item> body </item>
<item> component </item>
<item> entity </item>
<item> file </item>
<item> package </item>
<item> library </item>
<item> generic </item>
<item> generate </item>
<item> function </item>
<item> variable </item>
<item> signal </item>
<item> record </item>
<item> procedure </item>
<item> process </item>
<item> port </item>
<item> use </item>
<item> is </item>
<item> ENTITY </item>
<item> MAP </item>
<item> ARCHITECTURE </item>
<item> ARRAY </item>
<item> ATTRIBUTE </item>
<item> BODY </item>
<item> COMPONENT </item>
<item> ENTITY </item>
<item> FILE </item>
<item> PACKAGE </item>
<item> LIBRARY </item>
<item> GENERIC </item>
<item> GENERATE </item>
<item> FUNCTION </item>
<item> VARIABLE </item>
<item> SIGNAL </item>
<item> RECORD </item>
<item> PROCEDURE </item>
<item> PROCESS </item>
<item> PORT </item>
<item> USE </item>
<item> IS </item>
</list>
<list name="keywords">
<item> access </item>
<item> abs </item>
<item> alias </item>
<item> all </item>
<item> assert </item>
<item> block </item>
<item> buffer </item>
<item> bus </item>
<item> configuration </item>
<item> constant </item>
<item> disconnect </item>
<item> exit </item>
<item> function </item>
<item> group </item>
<item> guarded </item>
<item> impure </item>
<item> inertial </item>
<item> label </item>
<item> linkage </item>
<item> literal </item>
<item> loop </item>
<item> new </item>
<item> null </item>
<item> on </item>
<item> open </item>
<item> package </item>
<item> postponed </item>
<item> pure </item>
<item> range </item>
<item> register </item>
<item> reject </item>
<item> return </item>
<item> rol </item>
<item> ror </item>
<item> select </item>
<item> severity </item>
<item> shared </item>
<item> sla </item>
<item> sli </item>
<item> sra </item>
<item> srl </item>
<item> subtype </item>
<item> transport </item>
<item> type </item>
<item> unaffected </item>
<item> units </item>
<item> ACCESS </item>
<item> ABS </item>
<item> ALIAS </item>
<item> ALL </item>
<item> ASSERT </item>
<item> BLOCK </item>
<item> BUFFER </item>
<item> BUS </item>
<item> CONFIGURATION </item>
<item> CONSTANT </item>
<item> DISCONNECT </item>
<item> EXIT </item>
<item> FUNCTION </item>
<item> GROUP </item>
<item> GUARDED </item>
<item> IMPURE </item>
<item> INERTIAL </item>
<item> LABEL </item>
<item> LINKAGE </item>
<item> LITERAL </item>
<item> LOOP </item>
<item> NEW </item>
<item> NULL </item>
<item> ON </item>
<item> OPEN </item>
<item> PACKAGE </item>
<item> POSTPONED </item>
<item> PURE </item>
<item> RANGE </item>
<item> REGISTER </item>
<item> REJECT </item>
<item> RETURN </item>
<item> ROL </item>
<item> ROR </item>
<item> SELECT </item>
<item> SEVERITY </item>
<item> SHARED </item>
<item> SLA </item>
<item> SLI </item>
<item> SRA </item>
<item> SRL </item>
<item> SUBTYPE </item>
<item> TRANSPORT </item>
<item> TYPE </item>
<item> UNAFFECTED </item>
<item> UNITS </item>
</list>
<list name="boolean">
<item> and </item>
<item> xnor </item>
<item> xor </item>
<item> nand </item>
<item> nor </item>
<item> not </item>
<item> or </item>
<item> AND </item>
<item> XNOR </item>
<item> XOR </item>
<item> NAND </item>
<item> NOR </item>
<item> NOT </item>
<item> OR </item>
</list>
<list name="direction">
<item> in </item>
<item> out </item>
<item> inout </item>
<item> downto </item>
<item> to </item>
<item> IN </item>
<item> OUT </item>
<item> INOUT </item>
<item> DOWNTO </item>
<item> TO </item>
</list>
<list name="function">
<item> after </item>
<item> begin </item>
<item> case </item>
<item> else </item>
<item> elsif </item>
<item> end </item>
<item> for </item>
<item> if </item>
<item> mod </item>
<item> next </item>
<item> others </item>
<item> then </item>
<item> until </item>
<item> wait </item>
<item> when </item>
<item> while </item>
<item> with </item>
<item> AFTER </item>
<item> BEGIN </item>
<item> CASE </item>
<item> ELSE </item>
<item> ELSIF </item>
<item> END </item>
<item> FOR </item>
<item> IF </item>
<item> MOD </item>
<item> NEXT </item>
<item> OTHERS </item>
<item> THEN </item>
<item> UNTIL </item>
<item> WAIT </item>
<item> WHEN </item>
<item> WHILE </item>
<item> WITH </item>
</list>
<list name="library">
<item> ieee </item>
<item> std_logic_1164 </item>
<item> numeric_bit </item>
<item> numeric_std </item>
<item> std_logic_arith </item>
<item> std_logic_unsigned </item>
<item> std_logic_signed </item>
<item> std_logic_misc </item>
<item> IEEE </item>
<item> STD_LOGIC_1164 </item>
<item> NUMERIC_BIT </item>
<item> NUMERIC_STD </item>
<item> STD_LOGIC_ARITH </item>
<item> STD_LOGIC_UNSIGNED </item>
<item> STD_LOGIC_SIGNED </item>
<item> STD_LOGIC_MISC </item>
</list>
<list name="types">
<item> bit </item>
<item> bit_vector </item>
<item> character </item>
<item> boolean </item>
<item> integer </item>
<item> real </item>
<item> time </item>
<item> string </item>
<item> severity_level </item>
<item> positive </item>
<item> natural </item>
<item> signed </item>
<item> unsigned </item>
<item> line </item>
<item> text </item>
<item> std_logic </item>
<item> std_logic_vector </item>
<item> std_ulogic </item>
<item> std_ulogic_vector </item>
<item> qsim_state </item>
<item> qsim_state_vector </item>
<item> qsim_12state </item>
<item> qsim_12state_vector </item>
<item> qsim_strength </item>
<item> mux_bit </item>
<item> mux_vector </item>
<item> reg_bit </item>
<item> reg_vector </item>
<item> wor_bit </item>
<item> wor_vector </item>
<item> BIT </item>
<item> BIT_VECTOR </item>
<item> CHARACTER </item>
<item> BOOLEAN </item>
<item> INTEGER </item>
<item> REAL </item>
<item> TIME </item>
<item> STRING </item>
<item> SEVERITY_LEVEL </item>
<item> POSITIVE </item>
<item> NATURAL </item>
<item> SIGNED </item>
<item> UNSIGNED </item>
<item> LINE </item>
<item> TEXT </item>
<item> STD_LOGIC </item>
<item> STD_LOGIC_VECTOR </item>
<item> STD_ULOGIC </item>
<item> STD_ULOGIC_VECTOR </item>
<item> QSIM_STATE </item>
<item> QSIM_STATE_VECTOR </item>
<item> QSIM_12STATE </item>
<item> QSIM_12STATE_VECTOR </item>
<item> QSIM_STRENGTH </item>
<item> MUX_BIT </item>
<item> MUX_VECTOR </item>
<item> REG_BIT </item>
<item> REG_VECTOR </item>
<item> WOR_BIT </item>
<item> WOR_VECTOR </item>
</list>
<contexts>
<context name="normal" attribute="Normal Text" lineEndContext="#stay">
<keyword attribute="Declaration" context="#stay" \
String="declaration"/> <keyword attribute="Keywords" context="#stay" \
String="keywords"/> <keyword attribute="Boolean" context="#stay" String="boolean"/>
<keyword attribute="Direction" context="#stay" String="direction"/>
<keyword attribute="Function" context="#stay" String="function"/>
<keyword attribute="Library" context="#stay" String="library"/>
<keyword attribute="Data Type" context="#stay" String="types"/>
<Detect2Chars attribute="Comment" context="comment" char="-" \
char1="-" /> <Int attribute="Integer" context="#stay" />
<HlCChar attribute="Bit" context="#stay" />
<DetectChar attribute="Vector" context="string" char=""" />
<AnyChar attribute="Operator" context="#stay" \
String="[&><=:+\-*\/|]().,;" />
<DetectChar attribute="Attribute" context="attribute" char="'" />
</context>
<context name="comment" attribute="Comment" lineEndContext="#pop" />
<context name="string" attribute="Vector" lineEndContext="#stay" >
<DetectChar attribute="Vector" context="#pop" char=""" />
</context>
<context name="attribute" attribute="Attribute" lineEndContext="#pop">
<DetectChar attribute="Attribute" context="quot in att" char=""" \
/>
<DetectChar attribute="Normal Text" context="#pop" char=" " />
<AnyChar attribute="Attribute" context="#pop" String=")=<>" />
</context>
<context name="quot in att" attribute="Attribute" lineEndContext="#stay">
<DetectChar attribute="Attribute" context="#pop" char=""" />
</context>
</contexts>
<itemDatas>
<itemData name="Normal Text" defStyleNum="dsNormal" />
<itemData name="Declaration" defStyleNum="dsString" />
<itemData name="Keywords" defStyleNum="dsDecVal" />
<itemData name="Boolean" defStyleNum="dsBaseN" />
<itemData name="Direction" defStyleNum="dsOthers" />
<itemData name="Function" defStyleNum="dsFloat" />
<itemData name="Library" defStyleNum="dsAlert" />
<itemData name="Data Type" defStyleNum="dsDataType" />
<itemData name="Comment" defStyleNum="dsComment" />
<itemData name="Integer" defStyleNum="dsDecVal" />
<itemData name="Bit" defStyleNum="dsChar" />
<itemData name="Vector" defStyleNum="dsString" />
<itemData name="Operator" defStyleNum="dsOthers" />
<itemData name="Attribute" defStyleNum="dsBaseN" />
</itemDatas>
</highlighting>
<general>
<comments>
<comment name="singleLine" start="--" />
</comments>
<keywords casesensitive="1" />
</general>
</language>
["ffaria.vcf" (text/x-vcard)]
["BitDefender.txt" (text/plain)]
--
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