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List: xen-devel
Subject: [Xen-devel] [PATCH v2] xen/arm: Handle unimplemented VGICv3 dist registers as RAZ/WI
From: Jeff Kubascik <jeff.kubascik () dornerworks ! com>
Date: 2020-01-31 20:10:46
Message-ID: 20200131201046.44996-1-jeff.kubascik () dornerworks ! com
[Download RAW message or body]
Per the ARM Generic Interrupt Controller Architecture Specification (ARM
IHI 0069E), reserved registers should generally be treated as RAZ/WI.
To simplify the VGICv3 design and improve guest compatability, treat the
default case for GICD registers as read_as_zero/write_ignore.
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
---
xen/arch/arm/vgic-v3.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 422b94f902..8d0856ac33 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -1250,9 +1250,9 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info,
goto read_impl_defined;
default:
- printk(XENLOG_G_ERR "%pv: vGICD: unhandled read r%d offset %#08x\n",
- v, dabt.reg, gicd_reg);
- return 0;
+ /* Since reserved registers should be read-as-zero, make this the
+ * default case */
+ goto read_as_zero;
}
bad_width:
@@ -1435,10 +1435,9 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info,
goto write_impl_defined;
default:
- printk(XENLOG_G_ERR
- "%pv: vGICD: unhandled write r%d=%"PRIregister" offset %#08x\n",
- v, dabt.reg, r, gicd_reg);
- return 0;
+ /* Since reserved registers should be write-ignore, make this the
+ * default case */
+ goto write_ignore;
}
bad_width:
--
2.17.1
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