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List:       xen-cvs
Subject:    [Xen-changelog] [xen stable-4.7] x86: MISALIGNSSE feature depends on SSE
From:       patchbot () xen ! org
Date:       2016-10-27 10:23:23
Message-ID: E1bzhqF-0000Ig-Ba () xenbits ! xenproject ! org
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commit 5bcf70dfaf71106970f6e256d2fe4e5158721ab6
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Oct 25 17:13:09 2016 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Oct 25 17:13:09 2016 +0200

    x86: MISALIGNSSE feature depends on SSE
    
    Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-acked-by: Wei Liu <wei.liu2@citrix.com>
    master commit: b4ca886ab18ddcc729c1bc3d730ab078508d7ce3
    master date: 2016-10-24 17:34:17 +0200
---
 xen/tools/gen-cpuid.py | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 92bbcdc..7135fd2 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -196,8 +196,9 @@ def crunch_numbers(state):
 
         # SSE is taken to mean support for the %XMM registers as well as the
         # instructions.  Several futher instruction sets are built on core
-        # %XMM support, without specific inter-dependencies.
-        SSE: [SSE2, SSE3, SSSE3, SSE4A,
+        # %XMM support, without specific inter-dependencies.  Additionally
+        # AMD has a special mis-alignment sub-mode.
+        SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE,
               AESNI, SHA],
 
         # SSE2 was re-specified as core instructions for 64bit.
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.7

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