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List:       usrp-users
Subject:    [USRP-users] Re: Simulation after synthesis or implementation
From:       Wade Fife <wade.fife () ettus ! com>
Date:       2022-10-26 15:44:43
Message-ID: CAFche=jGh4jqqr2RDubCu6t=LLfZjenCDTQSpGocNkwqgJp_bw () mail ! gmail ! com
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Hi Adri=C3=A1n,

It is possible to do a post-synthesis simulation, but that's an advanced
topic and I wouldn't recommend it unless you suspect you've found a bug in
Vivado synthesis. There's no way to do a post-implementation simulation
that I know of.

If you want to do a normal simulation and write your own HDL testbench
(this standard best practice and is what I recommend), you can take a look
at:

https://files.ettus.com/manual/md_usrp3_simulation.html

There are also lots of examples of simulations in the UHD repo. Search for
files named *_tb.sv for examples.

Another option for debugging is to use an ILA (Integrated Logic Analyzer).
This is usually a last resort, when you have written a testbench but still
haven't found any issues. For instructions, see:

https://kb.ettus.com/Debugging_FPGA_images

Wade

On Wed, Oct 26, 2022 at 5:54 AM <adri96roll@gmail.com> wrote:

> Hi everyone,
>
>
> I was wondering if it is possible to make a simulation,, and how, after
> sythesis or implementation because i am not getting the results that i wa=
s
> expecting and i don=C2=B4t know why.
>
>
> Thanks in advance.
>
>
> Adri=C3=A1n Campos
> _______________________________________________
> USRP-users mailing list -- usrp-users@lists.ettus.com
> To unsubscribe send an email to usrp-users-leave@lists.ettus.com
>

[Attachment #5 (text/html)]

<div dir="ltr"><div>Hi 
Adrián,</div><div><br></div><div>It is possible to do a post-synthesis simulation, \
but that&#39;s an advanced topic and I wouldn&#39;t recommend it unless you suspect \
you&#39;ve found a bug in Vivado synthesis. There&#39;s no way to do a \
post-implementation simulation that I know of. <br></div><div><br></div><div>If you \
want to do a normal simulation and write your own HDL testbench (this standard best \
practice and is what I recommend), you can take a look \
at:</div><div><br></div><div><a \
href="https://files.ettus.com/manual/md_usrp3_simulation.html">https://files.ettus.com/manual/md_usrp3_simulation.html</a></div><div><br></div><div>There \
are also lots of examples of simulations in the UHD repo. Search for files named *_<a \
href="http://tb.sv">tb.sv</a> for examples.</div><div><br></div><div>Another option \
for debugging is to use an ILA (Integrated Logic Analyzer). This is usually a last \
resort, when you have written a testbench but still haven&#39;t found any issues. For \
instructions, see:<br></div><div><br></div><div><a \
href="https://kb.ettus.com/Debugging_FPGA_images">https://kb.ettus.com/Debugging_FPGA_images</a></div><div><br></div><div>Wade \
<br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On \
Wed, Oct 26, 2022 at 5:54 AM &lt;<a \
href="mailto:adri96roll@gmail.com">adri96roll@gmail.com</a>&gt; \
wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px \
0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><p>Hi \
everyone,</p><p><br></p><p>I was wondering if it is possible to make a simulation,, \
and how, after sythesis or implementation because i am not getting the results that i \
was expecting and i don ´t know why.</p><p><br></p><p>Thanks in \
advance.</p><p><br></p><p>Adrián Campos</p>

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USRP-users mailing list -- <a href="mailto:usrp-users@lists.ettus.com" \
target="_blank">usrp-users@lists.ettus.com</a><br> To unsubscribe send an email to <a \
href="mailto:usrp-users-leave@lists.ettus.com" \
target="_blank">usrp-users-leave@lists.ettus.com</a><br> </blockquote></div>



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