[prev in list] [next in list] [prev in thread] [next in thread]
List: usrp-users
Subject: Re: [USRP-users] Header files cannot be opened upon trying to compile the FPGA image for b205mini
From: Varban Metodiev via USRP-users <usrp-users () lists ! ettus ! com>
Date: 2019-12-28 10:48:32
Message-ID: CAKA0MUjaeHuEaJWrpQB2aGRZfF9=MApK3oL9aPwrki-L+N5dpA () mail ! gmail ! com
[Download RAW message or body]
[Attachment #2 (multipart/alternative)]
Hi Marcus,
At first, I tried sourcing the "settings64.sh" file, as per the official
instructions:
Build Instructions (Xilinx ISE only)Makefile based Builder
- To add xtclsh to the PATH and to setup up the Xilinx build environment
run
- *source <install_dir>/Xilinx/14.7/ISE_DS/settings64.sh (64-bit
platform)*
However, I did not see the PATH variable being concatenated with the xtclsh
path. That is why I got the path from "which xtclsh" and manually appended
it to the PATH.
In both cases (with or without xtclpath present inside the PATH), I always
get the problem with opening the Verilog headers.
Do you have a specific shell that you
prepare for synthesis?
---> No, I am just using the official Linux VM installation of Xilinx ISE.
I keep the shell environment by default.
Regards,
Varban
On Sat, Dec 28, 2019 at 12:13 PM Marcus M=C3=BCller <marcus.mueller@ettus.c=
om>
wrote:
> Hi Varban,
>
> just a transient observation: your $PATH contains *a lot* of redundant
> ISE paths, as if some script kept recursively sourcing the xilinx
> settings. How are these set? Do you have a specific shell that you
> prepare for synthesis?
>
> Best regards,
> Marcus
> On Fri, 2019-12-27 at 12:47 +0000, Varban Metodiev via USRP-users
> wrote:
> > Hi,
> >
> > I am trying to compile the FPGA image for a b205mini as per the
> > official instructions. My environment looks like this:
> >
> > [ise@localhost b2xxmini]$ which xtclsh
> > /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh
> > [ise@localhost b2xxmini]$ pwd
> > /home/ise/USRP/fpga/usrp3/top/b2xxmini
> >
> > [ise@localhost b2xxmini]$ echo $PATH
> > /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sys
> > gen/util:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:/opt/Xilinx/14.7/ISE_
> > DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xil
> > inx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microbl
> > aze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-
> > eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/
> > 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili
> > nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X
> > ilinx/14.7/ISE_DS/common/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/li
> > n64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/I
> > SE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx
> > /14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt
> > /Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_D
> > S/EDK/gnu/powerpc-
> > eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/
> > 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili
> > nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X
> > ilinx/14.7/ISE_DS/common/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/li
> > n64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/I
> > SE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx
> > /14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt
> > /Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_D
> > S/EDK/gnu/powerpc-
> > eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/
> > 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili
> > nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X
> > ilinx/14.7/ISE_DS/common/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/li
> > n64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/I
> > SE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx
> > /14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt
> > /Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_D
> > S/EDK/gnu/powerpc-
> > eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/
> > 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili
> > nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X
> > ilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt-
> > 3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin:
> > /home/ise/bin:/home/ise/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh
> >
> >
> > Upon starting the "make B205mini", the header files inside
> > /fpga/usrp3/lib/ cannot be accessed.
> >
> > INFO:ProjectMgmt - Include file found:
> > '/home/ise/USRP/fpga/usrp3/lib/wishbone/i2c_master_defines.v' in
> > file
> > "/home/ise/USRP/fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v"
> > line 73
> > ERROR:ProjectMgmt - 1 error(s) found while parsing design hierarchy.
> > WARNING:ProjectMgmt - Circular Reference:
> > work:Module|cam_priority_encoder
> > > > > Adding source to project:
> > > > > /home/ise/USRP/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v
> > INFO:HDLCompiler:1845 - Analyzing Verilog file
> > "/home/ise/USRP/fpga/usrp3/lib/packet_proc/source_flow_control.v"
> > into
> > library work
> > ERROR:HDLCompiler:281 -
> > "/home/ise/USRP/fpga/usrp3/lib/packet_proc/source_flow_control.v"
> > Line 55:
> > Cannot open include file "chdr_pkt_types.vh".
> > INFO:HDLCompiler:1845 - Analyzing Verilog file
> > "/home/ise/USRP/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v" into
> > library work
> > ERROR:ProjectMgmt - 1 error(s) found while parsing design hierarchy.
> > WARNING:ProjectMgmt - Circular Reference:
> > work:Module|cam_priority_encoder
> > > > > Adding source to project:
> > > > > /home/ise/USRP/fpga/usrp3/lib/timing/time_compare.v
> > INFO:TclTasksC - File
> > "/home/ise/USRP/fpga/usrp3/lib/timing/time_compare.v" is
> > already present in the project
> >
> > May you please advise how add the search path correctly? Or maybe I
> > have missed something in the environment configuration?
> >
> > Regards,
> > Varban
> >
> > _______________________________________________
> > USRP-users mailing list
> > USRP-users@lists.ettus.com
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
[Attachment #5 (text/html)]
<div dir="ltr">Hi Marcus,<div><br></div><div>At first, I tried sourcing the \
"settings64.sh" file, as per the official instructions:</div><div><h2 \
style="margin-right:15px;color:rgb(0,0,0);font-family:Roboto,sans-serif">Build \
Instructions (Xilinx ISE only)</h2><h3 \
style="margin-right:15px;color:rgb(0,0,0);font-family:Roboto,sans-serif">Makefile \
based Builder</h3><ul \
style="color:rgb(0,0,0);font-family:Roboto,sans-serif;font-size:14px"><li>To add \
xtclsh to the PATH and to setup up the Xilinx build environment \
run<ul><li><b><code>source \
<install_dir>/Xilinx/14.7/ISE_DS/settings64.sh</code> (64-bit \
platform)</b></li></ul></li></ul><div><font color="#000000" face="Roboto, \
sans-serif"><span style="font-size:14px">However, I did not see the PATH variable \
being concatenated with the xtclsh path. That is why I got the path from "which \
xtclsh" and manually appended it to the \
PATH.</span></font></div></div><div><font color="#000000" face="Roboto, \
sans-serif"><span style="font-size:14px"><br></span></font></div><div><font \
color="#000000" face="Roboto, sans-serif"><span style="font-size:14px">In both cases \
(with or without xtclpath present inside the PATH), I always get the problem with \
opening the Verilog headers.</span></font></div><div><font color="#000000" \
face="Roboto, sans-serif"><span \
style="font-size:14px"><br></span></font></div><div>Do you have a specific shell that \
you<br>prepare for synthesis?<br></div><div>---> No, I am just using the official \
Linux VM installation of Xilinx ISE. I keep the shell environment by \
default.</div><div><font color="#000000" face="Roboto, sans-serif"><span \
style="font-size:14px"><br></span></font></div><div><font color="#000000" \
face="Roboto, sans-serif"><span \
style="font-size:14px">Regards,<br>Varban</span></font></div></div><br><div \
class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sat, Dec 28, 2019 at 12:13 \
PM Marcus Müller <<a \
href="mailto:marcus.mueller@ettus.com">marcus.mueller@ettus.com</a>> \
wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px \
0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Hi Varban,<br> <br>
just a transient observation: your $PATH contains *a lot* of redundant<br>
ISE paths, as if some script kept recursively sourcing the xilinx<br>
settings. How are these set? Do you have a specific shell that you<br>
prepare for synthesis?<br>
<br>
Best regards,<br>
Marcus<br>
On Fri, 2019-12-27 at 12:47 +0000, Varban Metodiev via USRP-users<br>
wrote:<br>
> Hi,<br>
> <br>
> I am trying to compile the FPGA image for a b205mini as per the<br>
> official instructions. My environment looks like this:<br>
> <br>
> [ise@localhost b2xxmini]$ which xtclsh<br>
> /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh<br>
> [ise@localhost b2xxmini]$ pwd<br>
> /home/ise/USRP/fpga/usrp3/top/b2xxmini<br>
> <br>
> [ise@localhost b2xxmini]$ echo $PATH<br>
> /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sys<br>
> gen/util:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:/opt/Xilinx/14.7/ISE_<br>
> DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xil<br>
> inx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microbl<br>
> aze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-<br>
> eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/<br>
> 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili<br>
> nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X<br>
> ilinx/14.7/ISE_DS/common/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/li<br>
> n64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/I<br>
> SE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx<br>
> /14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt<br>
> /Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_D<br>
> S/EDK/gnu/powerpc-<br>
> eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/<br>
> 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili<br>
> nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X<br>
> ilinx/14.7/ISE_DS/common/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/li<br>
> n64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/I<br>
> SE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx<br>
> /14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt<br>
> /Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_D<br>
> S/EDK/gnu/powerpc-<br>
> eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/<br>
> 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili<br>
> nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X<br>
> ilinx/14.7/ISE_DS/common/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/li<br>
> n64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/I<br>
> SE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx<br>
> /14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt<br>
> /Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_D<br>
> S/EDK/gnu/powerpc-<br>
> eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/<br>
> 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili<br>
> nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X<br>
> ilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt-<br>
> 3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin:<br>
> /home/ise/bin:/home/ise/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh<br>
> <br>
> <br>
> Upon starting the "make B205mini", the header files inside<br>
> /fpga/usrp3/lib/ cannot be accessed.<br>
> <br>
> INFO:ProjectMgmt - Include file found:<br>
> '/home/ise/USRP/fpga/usrp3/lib/wishbone/i2c_master_defines.v' \
in<br> > file<br>
> "/home/ise/USRP/fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v"<br>
> line 73<br>
> ERROR:ProjectMgmt - 1 error(s) found while parsing design hierarchy.<br>
> WARNING:ProjectMgmt - Circular Reference:<br>
> work:Module|cam_priority_encoder<br>
> > > > Adding source to project:<br>
> > > > /home/ise/USRP/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v<br>
> INFO:HDLCompiler:1845 - Analyzing Verilog file<br>
> "/home/ise/USRP/fpga/usrp3/lib/packet_proc/source_flow_control.v"<br>
> into<br>
> library work<br>
> ERROR:HDLCompiler:281 -<br>
> "/home/ise/USRP/fpga/usrp3/lib/packet_proc/source_flow_control.v"<br>
> Line 55:<br>
> Cannot open include file "chdr_pkt_types.vh".<br>
> INFO:HDLCompiler:1845 - Analyzing Verilog file<br>
> "/home/ise/USRP/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v" \
into<br> > library work<br>
> ERROR:ProjectMgmt - 1 error(s) found while parsing design hierarchy.<br>
> WARNING:ProjectMgmt - Circular Reference:<br>
> work:Module|cam_priority_encoder<br>
> > > > Adding source to project:<br>
> > > > /home/ise/USRP/fpga/usrp3/lib/timing/time_compare.v<br>
> INFO:TclTasksC - File<br>
> "/home/ise/USRP/fpga/usrp3/lib/timing/time_compare.v" is<br>
> already present in the project<br>
> <br>
> May you please advise how add the search path correctly? Or maybe I<br>
> have missed something in the environment configuration?<br>
> <br>
> Regards,<br>
> Varban<br>
> <br>
> _______________________________________________<br>
> USRP-users mailing list<br>
> <a href="mailto:USRP-users@lists.ettus.com" \
target="_blank">USRP-users@lists.ettus.com</a><br> > <a \
href="http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com" \
rel="noreferrer" target="_blank">http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com</a><br>
<br>
</blockquote></div>
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[prev in list] [next in list] [prev in thread] [next in thread]
Configure |
About |
News |
Add a list |
Sponsored by KoreLogic