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List: usrp-users
Subject: Re: [USRP-users] noc_block_siggen, sample rate control
From: Walter Maguire via USRP-users <usrp-users () lists ! ettus ! com>
Date: 2016-10-31 23:06:40
Message-ID: 94566c5e-175a-6903-b0c8-2f8f2ddd8d8f () iinet ! net ! au
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Hi Sugandha,
I think the ce_clk rate is fixed at a value to be determined. I think
the method for setting the frequency is potentially not correct as follows.
phase_inc = -8192*2*frequency/samp_rate. Lets assume the ce_rate is set
to 1MHz and does not change when the samp_rate is changed.
This means that if the samp_rate is changed from 1MHz to 10MHz then the
phase_inc is decreased which results in a lower frequency wave from.
This gives the impression that a higher sample rate is used but this is
not correct. What has actually taken place is a reduction in the wave
frequency. Probably fine for simulation but not for real world
application.
Regards
Walter
On 1/11/2016 8:25 AM, Sugandha Gupta wrote:
> Hey Walter
>
> Did you use the DUC in this to get the correct sample rate?
> So the DUC block should convert from 1e6 to 200e6. The calculation
> will then change to:
>
> (163/16834) * 1 MHz = 10kHz.
>
> I hope this helps.
>
>
> On Sun, Oct 30, 2016 at 11:31 PM, Walter Maguire via USRP-users
> <usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>> wrote:
>
> Hi All,
>
> If I look at the file noc_block_siggen.v the sine_tone has its
> clock set to ce_clk. If I recall correctly this clock is set to
> 200MHz.
>
> ////////////////////////////////////////////////////////////
> //
> // Sine_tone Block
> //
> ////////////////////////////////////////////////////////////
> sine_tone #(.WIDTH(32), .SR_PHASE_INC_ADDR(SR_PHASE_INC),
> .SR_CARTESIAN_ADDR(SR_CARTESIAN)) sine_tone_inst (
> .clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum),
> .enable(1'b1),
> .set_stb(set_stb), .set_data(set_data), .set_addr(set_addr),
> .o_tdata(s_axis_sine_tdata), .o_tlast(),
> .o_tvalid(s_axis_sine_tvalid), .o_tready(s_axis_sine_tready));
>
> Now looking at the UHD block xml file siggen.xml, like the FPGA
> noc_block_siggen.v suggests there is no SR register for the sample
> rate. However, if you look at the file uhd_rfnoc_siggen.xml which
> is used by GRC there is a sample rate specified as per
>
> <param>
> <name>Sample Rate</name>
> <key>samp_rate</key>
> <value>10000000</value>
> <type>real</type>
> </param>
>
> It looks like the only place this sample rate is used is on the
> lines in the grc block file uhd_rfnoc_siggen.xml
>
> self.$(id).set_arg("frequency", ((2*$frequency)/$samp_rate))
> <callback>set_arg("frequency",
> ((2*$frequency)/$samp_rate))</callback>
>
> Regarding the calculation of the desired phase_inc from the
> frequency the formula appears to be
>
> <arg>
> <name>frequency</name>
> <type>double</type>
> <value>0.1</value>
> <check>GE($frequency, -1.0) AND LE($frequency, 1.0)</check>
> <check_message>Invalid frequency.</check_message>
> <action>SR_WRITE("FREQ", IROUND(MULT(-8192.0,
> $frequency)))</action>
> </arg>
>
> where the frequency is
> Are these the calculations
>
> So lets say frequency = 10k, samp_rate = 1M then frequency sent to
> UHD block XML = 20k/1M = 0.02
>
> UHD block xml to FPGA Register = -8192*0.02 = -163.84
>
> POS_ROLLOVER = 2^13 = 8192
> NEG_ROLLOVER = -2^13 = -8192
>
> Therefore will the frequency out be
>
> (163/8192) * 200MHz = 4MHz and not 10k.
>
> Could you please elaborate on how the frequency generated relates
> to the 200MHz ce_clk.
>
> Does the samp_rate need to be set to 200MHz.
>
> Regards
>
> Walter
>
>
>
>
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> <http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com>
>
>
>
>
> --
> Sugandha Gupta
> Staff Software Engineer
> Ettus Research
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<p>Hi Sugandha,</p>
<p>I think the ce_clk rate is fixed at a value to be determined.
I think the method for setting the frequency is potentially not
correct as follows.</p>
<p>phase_inc = -8192*2*frequency/samp_rate. Lets assume the ce_rate
is set to 1MHz and does not change when the samp_rate is changed.<br>
</p>
<p>This means that if the samp_rate is changed from 1MHz to 10MHz
then the phase_inc is decreased which results in a lower frequency
wave from. This gives the impression that a higher sample rate is
used but this is not correct. What has actually taken place is a
reduction in the wave frequency. Probably fine for simulation
but not for real world application.</p>
<p>Regards</p>
<p><br>
</p>
<p>Walter<br>
</p>
<br>
<div class="moz-cite-prefix">On 1/11/2016 8:25 AM, Sugandha Gupta
wrote:<br>
</div>
<blockquote
cite="mid:CAG_kd14QrLGQrG-v2G4tD+D=sMJJxXL8A0eSBgNzL2tFEiFJ1g@mail.gmail.com"
type="cite">
<div dir="ltr">Hey Walter
<div><br>
</div>
<div>Did you use the DUC in this to get the correct sample rate?</div>
<div>So the DUC block should convert from 1e6 to 200e6. The
calculation will then change to: <br>
</div>
<div><br>
</div>
<div>(163/16834) * 1 MHz = 10kHz. </div>
<div><br>
</div>
<div>I hope this helps. </div>
<div><br>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Sun, Oct 30, 2016 at 11:31 PM,
Walter Maguire via USRP-users <span dir="ltr"><<a
moz-do-not-send="true"
href="mailto:usrp-users@lists.ettus.com" \
target="_blank">usrp-users@lists.ettus.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000"> Hi All,<br>
<br>
If I look at the file noc_block_siggen.v the sine_tone
has its clock set to ce_clk. If I recall correctly this
clock is set to 200MHz.<br>
<br>
<font \
color="#000099">/////////////////////////////<wbr>//////////////////////////////<wbr>/<br>
//<br>
// Sine_tone Block<br>
//<br>
//////////////////////////////<wbr>//////////////////////////////<br>
sine_tone #(.WIDTH(32), .SR_PHASE_INC_ADDR(SR_PHASE_<wbr>INC),
.SR_CARTESIAN_ADDR(SR_<wbr>CARTESIAN)) sine_tone_inst
(<br>
.clk(ce_clk), .reset(ce_rst),
.clear(clear_tx_seqnum), .enable(1'b1),<br>
.set_stb(set_stb), .set_data(set_data),
.set_addr(set_addr),<br>
.o_tdata(s_axis_sine_tdata), .o_tlast(),
.o_tvalid(s_axis_sine_tvalid),
.o_tready(s_axis_sine_tready))<wbr>;<br>
<br>
</font>Now looking at the UHD block xml file siggen.xml,
like the FPGA noc_block_siggen.v suggests there is no SR
register for the sample rate. However, if you look at
the file uhd_rfnoc_siggen.xml which is used by GRC there
is a sample rate specified as per<br>
<br>
<param><br>
<name>Sample Rate</name><br>
<key>samp_rate</key><br>
<value>10000000</value><br>
<type>real</type><br>
</param><br>
<br>
It looks like the only place this sample rate is used is
on the lines in the grc block file uhd_rfnoc_siggen.xml<br>
<br>
self.$(id).set_arg("frequency"<wbr>,
((2*$frequency)/$samp_rate))<br>
<callback>set_arg("frequency"<wbr>,
((2*$frequency)/$samp_rate))</<wbr>callback><br>
<br>
Regarding the calculation of the desired phase_inc from
the frequency the formula appears to be<br>
<br>
<arg><br>
<name>frequency</name><br>
<type>double</type><br>
<value>0.1</value><br>
<check>GE($frequency, -1.0) AND
LE($frequency, 1.0)</check><br>
<check_message>Invalid
frequency.</check_message><br>
<action>SR_WRITE("FREQ",
IROUND(MULT(-8192.0, $frequency)))</action><br>
</arg><br>
<br>
where the frequency is <br>
Are these the calculations <br>
<br>
So lets say frequency = 10k, samp_rate = 1M then
frequency sent to UHD block XML = 20k/1M = 0.02<br>
<br>
UHD block xml to FPGA Register = -8192*0.02 = -163.84<br>
<br>
POS_ROLLOVER = 2^13 = 8192<br>
NEG_ROLLOVER = -2^13 = -8192<br>
<br>
Therefore will the frequency out be<br>
<br>
(163/8192) * 200MHz = 4MHz and not 10k.<br>
<br>
Could you please elaborate on how the frequency
generated relates to the 200MHz ce_clk.<br>
<br>
Does the samp_rate need to be set to 200MHz.<br>
<br>
Regards<span class="HOEnZb"><font color="#888888"><br>
<br>
Walter<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
</font></span></div>
<br>
______________________________<wbr>_________________<br>
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<br>
</blockquote>
</div>
<br>
<br clear="all">
<div><br>
</div>
-- <br>
<div class="gmail_signature" data-smartmail="gmail_signature">
<div dir="ltr">
<div>Sugandha Gupta</div>
Staff Software Engineer
<div>Ettus Research</div>
</div>
</div>
</div>
</div>
</blockquote>
<br>
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