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List: usrp-users
Subject: Re: [USRP-users] =?utf-8?q?HDL_code_for_Ettus_Boards=EF=BC=88B210_an?=
From: Marcus_Müller via USRP-users <usrp-users () lists ! ettus ! com>
Date: 2016-10-26 13:24:27
Message-ID: 940f1079-c4c0-7266-6cce-1c4367001d8d () ettus ! com
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Hi Zhuimengren,
you've already gotten a response (two responses, in fact) from me
yesterday; did that not get through?
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-October/022372.html
Best regards,
Marcus
On 10/26/2016 07:51 AM, zhuimengren via USRP-users wrote:
> Good evening,
> We are developing a receiver and we want to implement it on USRP
> B210 and USRP B200 boards Ettus.
> I need to know if it is there available some project like these,
> wroten in VHDL codes. We are highly interested in cores programmable
> and customizable, and these can be adapted our needs. By other hand,
> we would like to integrate to design, using the Xilinx's software
> tools. Is there some core like this available? Could you send us some
> information about this one, please? Most of the literature I've been
> reading seems to focus on using GNU Radio or some other front end to
> talk to the board but our requirement is to programme directly with a
> bit file generated from ISE. We are very interesting VHDL/Verilog code
> to interface with the peripherals attached to the FPGA. Is the HDL
> code for interfacing with these peripherals published? Either way, do
> you have any suggestions on how one might proceed to building a custom
> design in ISE for B210. And we don't want to do great damage to main
> structure, we want to modify something base on FPGA. CAN we achieve it
> in ISE for B210?
> We want to get the time from GPS by GPSDO. How can we control the
> GPSDO? Can the FPGA get the time and data? and when we deal with the
> data, we can know the time when USRP receive. Do you have some
> suggestions on how one might build a custom design in ISE for B210? I
> will be grateful if you can send me information about this topic.
> Thank you so much for your attention.
> Best regards
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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<p>Hi Zhuimengren,<br>
</p>
you've already gotten a response (two responses, in fact) from me
yesterday; did that not get through?<br>
<br>
<a class="moz-txt-link-freetext" \
href="http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-October/022372. \
html">http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-October/022372.html</a><br>
<br>
Best regards,<br>
Marcus<br>
<div class="moz-cite-prefix">On 10/26/2016 07:51 AM, zhuimengren via
USRP-users wrote:<br>
</div>
<blockquote
cite="mid:159ff370.4e13.157ff8b8117.Coremail.bjcmcy@163.com"
type="cite">
<div
style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial">
<div
style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial">
<div
style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial">
<div>Good evening,<br>
We are developing a receiver and we want to implement
it on USRP B210 and USRP B200 boards Ettus. <br>
</div>
</div>
</div>
</div>
</blockquote>
<blockquote
cite="mid:159ff370.4e13.157ff8b8117.Coremail.bjcmcy@163.com"
type="cite">
<div
style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial">
<div
style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial">
<div
style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial">
<div>I need to know if it is there available some project
like these, wroten in VHDL codes. We are highly interested
in cores programmable and customizable, and these can be
adapted our needs. By other hand, we would like to
integrate to design, using the Xilinx's software tools. Is
there some core like this available? Could you send us
some information about this one, please? Most of the
literature I've been reading seems to focus on using GNU
Radio or some other front end to talk to the board but our
requirement is to programme directly with a bit file
generated from ISE. We are very interesting VHDL/Verilog
code to interface with the peripherals attached to the
FPGA. Is the HDL code for interfacing with these
peripherals published? Either way, do you have any
suggestions on how one might proceed to building a custom
design in ISE for B210. And we don't want to do great
damage to main structure, we want to modify something base
on FPGA. CAN we achieve it in ISE for B210? <br>
We want to get the time from GPS by GPSDO. How can we
control the GPSDO? Can the FPGA get the time and data?
and when we deal with the data, we can know the time when
USRP receive. Do you have some suggestions on how one
might build a custom design in ISE for B210? I will be
grateful if you can send me information about this topic.<br>
<pre>Thank you so much for your attention.
Best regards
</pre>
<br>
</div>
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<pre wrap="">_______________________________________________
USRP-users mailing list
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href="mailto:USRP-users@lists.ettus.com">USRP-users@lists.ettus.com</a> <a \
class="moz-txt-link-freetext" \
href="http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com">http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com</a>
</pre>
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<br>
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