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List: usrp-users
Subject: [USRP-users] =?gbk?q?HDL_code_for_Ettus_Boards=A3=A8B210_and_B200?= =?gbk?q?=A3=A9_AND_GPSDO?=
From: zhuimengren via USRP-users <usrp-users () lists ! ettus ! com>
Date: 2016-10-26 5:51:55
Message-ID: 159ff370.4e13.157ff8b8117.Coremail.bjcmcy () 163 ! com
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Good evening,
We are developing a receiver and we want to implement it on USRP B210 and USRP \
B200 boards Ettus. I need to know if it is there available some project like these, \
wroten in VHDL codes. We are highly interested in cores programmable and \
customizable, and these can be adapted our needs. By other hand, we would like to \
integrate to design, using the Xilinx's software tools. Is there some core like this \
available? Could you send us some information about this one, please? Most of the \
literature I've been reading seems to focus on using GNU Radio or some other front \
end to talk to the board but our requirement is to programme directly with a bit file \
generated from ISE. We are very interesting VHDL/Verilog code to interface with the \
peripherals attached to the FPGA. Is the HDL code for interfacing with these \
peripherals published? Either way, do you have any suggestions on how one might \
proceed to building a custom design in ISE for B210. And we don't want to do great \
damage to main structure, we want to modify something base on FPGA. CAN we achieve it \
in ISE for B210? We want to get the time from GPS by GPSDO. How can we control the \
GPSDO? Can the FPGA get the time and data? and when we deal with the data, we can \
know the time when USRP receive. Do you have some suggestions on how one might build \
a custom design in ISE for B210? I will be grateful if you can send me information \
about this topic.
Thank you so much for your attention.
Best regards
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<div style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial"><div \
style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial"><div \
style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial"><div>Good \
evening,<br> We are developing a receiver and we want to implement it on \
USRP B210 and USRP B200 boards Ettus. <br>I need to know if it is there available \
some project like these, wroten in VHDL codes. We are highly interested in cores \
programmable and customizable, and these can be adapted our needs. By other hand, we \
would like to integrate to design, using the Xilinx's software tools. Is there some \
core like this available? Could you send us some information about this one, please? \
Most of the literature I've been reading seems to focus on using GNU Radio or some \
other front end to talk to the board but our requirement is to programme directly \
with a bit file generated from ISE. We are very interesting VHDL/Verilog code to \
interface with the peripherals attached to the FPGA. Is the HDL code for interfacing \
with these peripherals published? Either way, do you have any suggestions on how one \
might proceed to building a custom design in ISE for B210. And we don't want to do \
great damage to main structure, we want to modify something base on FPGA. CAN we \
achieve it in ISE for B210? <br> We want to get the time from GPS by GPSDO. How \
can we control the GPSDO? Can the FPGA get the time and data? and when we \
deal with the data, we can know the time when USRP receive. Do you have some \
suggestions on how one might build a custom design in ISE for B210? I will be \
grateful if you can send me information about this topic.<br><pre>Thank you so much \
for your attention.<br>Best regards<br><br></pre><br></div><br><br><div \
style="position:relative;zoom:1"><br><div \
style="clear:both"></div></div></div><br><br><span \
title="neteasefooter"><p> </p></span></div><br><br><span \
title="neteasefooter"><p> </p></span></div><br><br><span \
title="neteasefooter"><p> </p></span>
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