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List: usrp-users
Subject: Re: [USRP-users] N210 FPGA Memory
From: Marcus_Müller via USRP-users <usrp-users () lists ! ettus ! com>
Date: 2016-05-26 18:59:08
Message-ID: 5747477C.3070008 () ettus ! com
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So in that case, sampling with more than 50MS/s doesn't give you any
additional info on the signal you're observing (which can be at most
40MHz wide. The oversampling effect of the 100MS/s ADC is that you get
improved SNR, and that's already happening with the DSP chain as is.
So, the only problem is that at 50MS/s, you can only do 8 bit sampling,
exactly due to the Gigabit bandwidth restriction. That limits your SNR;
there's quantization noise.
So the question is to what end you want to sample at 100MS/s – maybe we
can come up with something elegant that makes your application possible!
Best regards,
Marcus
On 26.05.2016 18:19, Topliff, Charles Alexander wrote:
>
> I am using the 40mhz SBX daugterboard. I also have access to the 40mhz
> CBX as well.
>
>
> Charles
>
> ------------------------------------------------------------------------
> *From:* USRP-users <usrp-users-bounces@lists.ettus.com> on behalf of
> Marcus Müller via USRP-users <usrp-users@lists.ettus.com>
> *Sent:* Thursday, May 26, 2016 10:51 AM
> *To:* usrp-users@lists.ettus.com
> *Subject:* Re: [USRP-users] N210 FPGA Memory
>
> Dear Charles,
>
> On 26.05.2016 16:08, Topliff, Charles Alexander via USRP-users wrote:
>> Hello All,
>>
>> I am interested in capturing samples at 100 MS/s using a USRP N210 at
>> a 16b (or 14-bit ADC) resolution. In the datasheet, it is mentioned
>> that the maximum host sampling rate N210 is capable of is 50MS/s at
>> 8bit resolution over Gigabit Ethernet. My understanding is that this
>> is a limitation imposed by the transfer speed over the Gigabit
>> ethernet interface.
> Exactly!
>>
>> To utilize the full potential of ADC sampling rate, what is the best
>> way to accumulate only a second (or half a second) worth of data?
>> Specifically, I would like to know if it is possible to use the FPGA
>> to synthesize memory & record 1 sec worth of samples (at 14b *
>> 100MS/s) to that. After recording, I would read it to the host at a
>> slower speed. Are there any constraints in that path?
> (14b/real + 14bit/image) * 100 MS/s * 1s = 2.800Gb = 350MB. That's
> much more than you could fit in any FPGA, and much more than the N210
> has in on-board RAM – in fact, the N210 already uses SRAM buffering
> itself on an 9Mbit SDRAM chip, but if I'm not mistaken, that's for TX
> data only.
>
> You could adapt that (it's called ext_fifo, IIRC) for your RX and get
> up to let's say 1/350s of buffering on the device.
>>
>> Is there a better way of handling this? Any suggestion is appreciated.
> On the N210, I'm not quite sure.
> One thing I wanted to ask was:
>
> Which daughterboard do you intend to use? All our daughterboards
> either have <= 40MHz bandwidth, so you gain nothing compared by using
> 100MS/s (compared to 50MS/s), according to Nyquist, or >=120 MHz
> bandwidth, so that they can't be used even at 100MS/s without aliasing.
> The only exception would be an BasicRX daughterboard with your own,
> custom, prefiltering that sufficiently band-limits the signal to
> something below 50MHz on each I and Q lane.
>
> Best regards,
> Marcus
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So in that case, sampling with more than 50MS/s doesn't give you any
additional info on the signal you're observing (which can be at most
40MHz wide. The oversampling effect of the 100MS/s ADC is that you
get improved SNR, and that's already happening with the DSP chain as
is. <br>
So, the only problem is that at 50MS/s, you can only do 8 bit
sampling, exactly due to the Gigabit bandwidth restriction. That
limits your SNR; there's quantization noise.<br>
<br>
So the question is to what end you want to sample at 100MS/s – maybe
we can come up with something elegant that makes your application
possible!<br>
<br>
Best regards,<br>
Marcus<br>
<br>
<div class="moz-cite-prefix">On 26.05.2016 18:19, Topliff, Charles
Alexander wrote:<br>
</div>
<blockquote cite="mid:1464279464095.38804@ku.edu" type="cite">
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style="display:none"><!--P{margin-top:0;margin-bottom:0;} p {margin-top:0;
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<p>I am using the 40mhz SBX daugterboard. I also have access to
the 40mhz CBX as well.</p>
<p><br>
</p>
<p>Charles<br>
</p>
<div style="color: rgb(33, 33, 33);">
<hr tabindex="-1" style="display:inline-block; width:98%">
<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt"
face="Calibri, sans-serif" color="#000000"><b>From:</b>
USRP-users <a class="moz-txt-link-rfc2396E" \
href="mailto:usrp-users-bounces@lists.ettus.com"><usrp-users-bounces@lists.ettus.com></a> \
on behalf of Marcus Müller via USRP-users
<a class="moz-txt-link-rfc2396E" \
href="mailto:usrp-users@lists.ettus.com"><usrp-users@lists.ettus.com></a><br> \
<b>Sent:</b> Thursday, May 26, 2016 10:51 AM<br>
<b>To:</b> <a class="moz-txt-link-abbreviated" \
href="mailto:usrp-users@lists.ettus.com">usrp-users@lists.ettus.com</a><br> \
<b>Subject:</b> Re: [USRP-users] N210 FPGA Memory</font> <div> </div>
</div>
<div>Dear Charles,<br>
<br>
<div class="moz-cite-prefix">On 26.05.2016 16:08, Topliff,
Charles Alexander via USRP-users wrote:<br>
</div>
<blockquote type="cite">
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<div style="margin:0"><font face="Calibri,sans-serif"
size="2"><span style="font-size:11pt"><font
color="black" size="3"><span style="font-size:12pt">Hello
All,</span></font></span></font></div>
<div style="margin:0"><font face="Calibri,sans-serif"
size="2"><span style="font-size:11pt"><font
color="black" size="3"><span style="font-size:12pt"> \
</span></font></span></font></div> <div style="margin:0"><font \
face="Calibri,sans-serif" size="2"><span style="font-size:11pt"><font
color="black" size="3"><span style="font-size:12pt">I
am interested in capturing samples at 100 MS/s
using a USRP N210 at a 16b (or 14-bit ADC)
resolution. In the datasheet, it is mentioned that
the maximum host sampling rate N210 is capable of
is 50MS/s at 8bit resolution over Gigabit
Ethernet. My understanding is that this is a
limitation imposed by the transfer speed over the
Gigabit ethernet interface.</span></font></span></font></div>
</blockquote>
<font size="3"><font face="Calibri,sans-serif">Exactly!</font></font><br>
<blockquote type="cite">
<div style="margin:0"><font face="Calibri,sans-serif"
size="2"><span style="font-size:11pt"><font
color="black" size="3"><span style="font-size:12pt"> \
</span></font></span></font></div> <div style="margin:0"><font \
face="Calibri,sans-serif" size="2"><span style="font-size:11pt"><font
color="black" size="3"><span style="font-size:12pt">To
utilize the full potential of ADC sampling rate,
what is the best way to accumulate only a second
(or half a second) worth of data? Specifically, I
would like to know if it is possible to use the
FPGA to synthesize memory & record 1 sec worth
of samples (at 14b * 100MS/s) to that. After
recording, I would read it to the host at a slower
speed. Are there any constraints in that \
path?</span></font></span></font></div> </blockquote>
<font size="3"><font face="Calibri,sans-serif">(14b/real +
14bit/image) * 100 MS/s * 1s = 2.800Gb = 350MB. That's
much more than you could fit in any FPGA, and much more
than the N210 has in on-board RAM – in fact, the N210
already uses SRAM buffering itself on an 9Mbit SDRAM chip,
but if I'm not mistaken, that's for TX data only.<br>
<br>
You could adapt that (it's called ext_fifo, IIRC) for your
RX and get up to let's say 1/350s of buffering on the
device.<br>
</font></font>
<blockquote type="cite">
<div style="margin:0"><font face="Calibri,sans-serif"
size="2"><span style="font-size:11pt"><font
color="black" size="3"><span style="font-size:12pt"> \
</span></font></span></font></div> <div style="margin:0"><font \
face="Calibri,sans-serif" size="2"><span style="font-size:11pt"><font
color="black" size="3"><span style="font-size:12pt">Is
there a better way of handling this? Any
suggestion is appreciated.</span></font></span></font></div>
</blockquote>
<font size="3"><font face="Calibri,sans-serif">On the N210,
I'm not quite sure.<br>
One thing I wanted to ask was:<br>
<br>
Which daughterboard do you intend to use? All our
daughterboards either have <= 40MHz bandwidth, so you
gain nothing compared by using 100MS/s (compared to
50MS/s), according to Nyquist, or >=120 MHz bandwidth,
so that they can't be used even at 100MS/s without
aliasing.<br>
The only exception would be an BasicRX daughterboard with
your own, custom, prefiltering that sufficiently
band-limits the signal to something below 50MHz on each I
and Q lane.<br>
<br>
Best regards,<br>
Marcus<br>
</font></font></div>
</div>
</blockquote>
<br>
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