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List: usrp-users
Subject: Re: [USRP-users] Compiling FPGA Source for B210
From: Sumit Kumar via USRP-users <usrp-users () lists ! ettus ! com>
Date: 2016-04-26 9:02:59
Message-ID: CAOExtcQ0A3OrGKMf2n_yhte_bjQ8yYOEC5VMGFqHiK0PisZAkA () mail ! gmail ! com
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Hi, Sorry I missed the mails. FPGA compilation went successful. I tried
uhd_fft and its working.
On Wed, Apr 6, 2016 at 5:56 PM, Jeremy Hershberger <
Jeremy.L.Hershberger.16@nd.edu> wrote:
> Every time you recompile the FPGA image from source it will take a long
> time (the exact time depends on how powerful your computer is)
>
> Did you try running the uhd_fft command with the default ettus image first
> to see if everything is working? You can run the images_downloader.py
> script to fetch precompiled fpga images to match your version of uhd
>
> -Jeremy
>
>
> On Wed, Apr 6, 2016 at 11:08 AM, James Humphries via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
> > No, they are the same value
> >
> > In verilog, the 16'h indicates a 16 bit hex value. The numbers that
> > follow are the contents to store in that parameter, 000E. Convert the hex
> > value to decimal and you should get 14 for both.
> >
> > -Trip
> >
> >
> >
> > On Wed, Apr 6, 2016 at 11:05 AM, Sumit Kumar <cogwsn@gmail.com> wrote:
> >
> > > So I see the following.
> > >
> > > static const boost::uint16_t B200_FPGA_COMPAT_NUM = 14;
> > >
> > > localparam COMPAT_MAJOR = 16'h000E;
> > >
> > > 14 and 16 !
> > >
> > > Does this mean that they are incompatible ?
> > >
> > >
> > > On Wed, Apr 6, 2016 at 4:05 PM, James Humphries <
> > > james.humphries@ettus.com> wrote:
> > >
> > > > Hi Sumit,
> > > >
> > > > You are correct, UHD checks the FPGA version number at run time to make
> > > > sure that the FPGA image and UHD have compatible features.
> > > >
> > > > Just so you know where to look in the FPGA code and UHD:
> > > >
> > > > For the B200 FPGA, the compatibility number is listed in b200_core.v as
> > > > COMPAT_MAJOR. It should be around line 81 as a hex value:
> > > >
> > > >
> > > > https://github.com/EttusResearch/fpga/blob/master/usrp3/top/b200/b200_core.v
> > > >
> > > > For UHD, the compatibility number is listed in b200_impl.h
> > > > as B200_FPGA_COMPAT_NUM. It should be around line 52 as an integer value:
> > > >
> > > >
> > > > https://github.com/EttusResearch/uhd/blob/2d68f228888807d0fd76c7b759ec39fd86523f67/host/lib/usrp/b200/b200_impl.hpp
> > > >
> > > > Let me know if you have any questions.
> > > >
> > > > -Trip
> > > >
> > > > On Wed, Apr 6, 2016 at 9:54 AM, Sumit Kumar via USRP-users <
> > > > usrp-users@lists.ettus.com> wrote:
> > > >
> > > > > Hello,
> > > > >
> > > > > Currently I have UHD_003.009.002-0-gf18abe54.
> > > > >
> > > > > I did a checkout and compiled the fpga source files for B210. But
> > > > > while doing uhd_fft, it gave me version mismatch error.
> > > > >
> > > > > I guess that firmware and fpga keep track of their version number and
> > > > > check it at run time. (Please correct if I am wrong)
> > > > >
> > > > > So I again did a checkout with commit -- f18abe54 and compiling the
> > > > > source. Its still one hour to get the result. Is it going to throw the same
> > > > > error ?
> > > > >
> > > > > I am using Xilinx ISE 14.7 (Licensed)
> > > > >
> > > > >
> > > > >
> > > > > --
> > > > > Sumit kumar
> > > > > Doctoral Student
> > > > > Eurecom, UPMC
> > > > > France
> > > > >
> > > > >
> > > > > _______________________________________________
> > > > > USRP-users mailing list
> > > > > USRP-users@lists.ettus.com
> > > > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> > > > >
> > > > >
> > > >
> > >
> > >
> > > --
> > > Sumit kumar
> > > Research Assistant
> > > Communication Research Center
> > > IIIT Hyderabad, India
> > > +91-7799081452
> > >
> > >
> >
> > _______________________________________________
> > USRP-users mailing list
> > USRP-users@lists.ettus.com
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> >
> >
>
--
--
Sumit kumar
Doctoral Student, UPMC
Eurecom, BIOT
France
[Attachment #5 (text/html)]
<div dir="ltr">Hi, Sorry I missed the mails. FPGA compilation went successful. I \
tried uhd_fft and its working. <div><br><div><br></div></div></div><div \
class="gmail_extra"><br><div class="gmail_quote">On Wed, Apr 6, 2016 at 5:56 PM, \
Jeremy Hershberger <span dir="ltr"><<a \
href="mailto:Jeremy.L.Hershberger.16@nd.edu" \
target="_blank">Jeremy.L.Hershberger.16@nd.edu</a>></span> wrote:<br><blockquote \
class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc \
solid;padding-left:1ex"><div dir="ltr"><div><div>Every time you recompile the FPGA \
image from source it will take a long time (the exact time depends on how powerful \
your computer is)<br><br></div>Did you try running the uhd_fft command with the \
default ettus image first to see if everything is working? You can run the \
images_downloader.py script to fetch precompiled fpga images to match your version of \
uhd<span class="HOEnZb"><font color="#888888"><br><br></font></span></div><span \
class="HOEnZb"><font \
color="#888888"><div>-Jeremy<br></div><div><br></div></font></span></div><div \
class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div \
class="gmail_quote">On Wed, Apr 6, 2016 at 11:08 AM, James Humphries via USRP-users \
<span dir="ltr"><<a href="mailto:usrp-users@lists.ettus.com" \
target="_blank">usrp-users@lists.ettus.com</a>></span> wrote:<br><blockquote \
class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc \
solid;padding-left:1ex"><div dir="ltr">No, they are the same \
value<div><br></div><div>In verilog, the 16'h indicates a 16 bit hex value. The \
numbers that follow are the contents to store in that parameter, 000E. Convert the \
hex value to decimal and you should get 14 for \
both.</div><div><br></div><div>-Trip</div><div><br></div><div><br></div></div><div><div><div \
class="gmail_extra"><br><div class="gmail_quote">On Wed, Apr 6, 2016 at 11:05 AM, \
Sumit Kumar <span dir="ltr"><<a href="mailto:cogwsn@gmail.com" \
target="_blank">cogwsn@gmail.com</a>></span> wrote:<br><blockquote \
class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc \
solid;padding-left:1ex"><div dir="ltr"><div>So I see the following. \
</div><div><br></div><div>static const boost::uint16_t B200_FPGA_COMPAT_NUM = 14; \
<div><br></div><div><span \
style="color:rgb(167,29,93);font-family:Consolas,'Liberation \
Mono',Menlo,Courier,monospace;font-size:12px;line-height:16.8px;white-space:pre-wrap">localparam</span><span \
style="color:rgb(51,51,51);font-family:Consolas,'Liberation \
Mono',Menlo,Courier,monospace;font-size:12px;line-height:16.8px;white-space:pre-wrap"> \
COMPAT_MAJOR </span><span \
style="color:rgb(167,29,93);font-family:Consolas,'Liberation \
Mono',Menlo,Courier,monospace;font-size:12px;line-height:16.8px;white-space:pre-wrap">=</span><span \
style="color:rgb(51,51,51);font-family:Consolas,'Liberation \
Mono',Menlo,Courier,monospace;font-size:12px;line-height:16.8px;white-space:pre-wrap"> \
</span><span style="color:rgb(0,134,179);font-family:Consolas,'Liberation \
Mono',Menlo,Courier,monospace;font-size:12px;line-height:16.8px;white-space:pre-wrap">16'h000E</span><span \
style="color:rgb(51,51,51);font-family:Consolas,'Liberation \
Mono',Menlo,Courier,monospace;font-size:12px;line-height:16.8px;white-space:pre-wrap">;</span></div></div><div><br></div><div>14 \
and 16 ! </div><div><br></div><div>Does this mean that they are incompatible ? \
</div><div><br></div><div><br></div><div class="gmail_extra"><div><div><div \
class="gmail_quote">On Wed, Apr 6, 2016 at 4:05 PM, James Humphries <span \
dir="ltr"><<a href="mailto:james.humphries@ettus.com" \
target="_blank">james.humphries@ettus.com</a>></span> wrote:<br><blockquote \
class="gmail_quote" style="margin:0px 0px 0px \
0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div \
dir="ltr">Hi Sumit,<div><br></div><div>You are correct, UHD checks the FPGA version \
number at run time to make sure that the FPGA image and UHD have compatible \
features.</div><div><br></div><div>Just so you know where to look in the FPGA code \
and UHD:</div><div><br></div><div>For the B200 FPGA, the compatibility number is \
listed in b200_core.v as COMPAT_MAJOR. It should be around line 81 as a hex \
value:</div><div><br></div><div><a \
href="https://github.com/EttusResearch/fpga/blob/master/usrp3/top/b200/b200_core.v" \
target="_blank">https://github.com/EttusResearch/fpga/blob/master/usrp3/top/b200/b200_core.v</a><br></div><div><br></div><div>For \
UHD, the compatibility number is listed in b200_impl.h as B200_FPGA_COMPAT_NUM. It \
should be around line 52 as an integer value:</div><div><br></div><div><a \
href="https://github.com/EttusResearch/uhd/blob/2d68f228888807d0fd76c7b759ec39fd86523f67/host/lib/usrp/b200/b200_impl.hpp" \
target="_blank">https://github.com/EttusResearch/uhd/blob/2d68f228888807d0fd76c7b759ec \
39fd86523f67/host/lib/usrp/b200/b200_impl.hpp</a><br></div><div><br></div><div>Let me \
know if you have any questions.</div><div><br></div><div>-Trip</div></div><div \
class="gmail_extra"><br><div class="gmail_quote"><div><div>On Wed, Apr 6, 2016 at \
9:54 AM, Sumit Kumar via USRP-users <span dir="ltr"><<a \
href="mailto:usrp-users@lists.ettus.com" \
target="_blank">usrp-users@lists.ettus.com</a>></span> \
wrote:<br></div></div><blockquote class="gmail_quote" style="margin:0px 0px 0px \
0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div><div><div \
dir="ltr">Hello, <div><br></div><div>Currently I have \
UHD_003.009.002-0-gf18abe54.</div><div><br></div><div>I did a checkout and compiled \
the fpga source files for B210. But while doing uhd_fft, it gave me version mismatch \
error. </div><div><br></div><div>I guess that firmware and fpga keep track of their \
version number and check it at run time. (Please correct if I am \
wrong)</div><div><br></div><div>So I again did a checkout with commit -- f18abe54 \
and compiling the source. Its still one hour to get the result. Is it going to throw \
the same error ? </div><div><br></div><div>I am using Xilinx ISE 14.7 \
(Licensed)</div><span><font \
color="#888888"><div><br></div><div><br></div><div><div><br></div>-- <br><div>Sumit \
kumar<br>Doctoral Student</div><div>Eurecom, UPMC</div><div>France<br><br></div> \
</div></font></span></div> \
<br></div></div>_______________________________________________<br> USRP-users \
mailing list<br> <a href="mailto:USRP-users@lists.ettus.com" \
target="_blank">USRP-users@lists.ettus.com</a><br> <a \
href="http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com" \
rel="noreferrer" target="_blank">http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com</a><br>
<br></blockquote></div><br></div>
</blockquote></div><br><br clear="all"><div><br></div></div></div><span><font \
color="#888888">-- <br><div>Sumit kumar<br>Research Assistant<br>Communication \
Research Center<br>IIIT Hyderabad, India<br><a href="tel:%2B91-7799081452" \
value="+917799081452" target="_blank">+91-7799081452</a><br><br></div> \
</font></span></div></div> </blockquote></div><br></div>
</div></div><br>_______________________________________________<br>
USRP-users mailing list<br>
<a href="mailto:USRP-users@lists.ettus.com" \
target="_blank">USRP-users@lists.ettus.com</a><br> <a \
href="http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com" \
rel="noreferrer" target="_blank">http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com</a><br>
<br></blockquote></div><br></div>
</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br><div \
class="gmail_signature"><div dir="ltr"><div><span \
style="color:rgb(136,136,136);font-size:12.8px">-- </span><br \
style="color:rgb(136,136,136);font-size:12.8px"><div \
style="color:rgb(136,136,136);font-size:12.8px">Sumit kumar<br>Doctoral Student, \
UPMC</div><div style="color:rgb(136,136,136);font-size:12.8px">Eurecom, \
BIOT</div><div style="color:rgb(136,136,136);font-size:12.8px">France</div><br></div></div></div>
</div>
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