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List: usrp-users
Subject: [USRP-users] x310 build timing issue
From: "Long, Jeffrey P. via USRP-users" <usrp-users () lists ! ettus ! com>
Date: 2016-01-28 15:23:08
Message-ID: SN1PR09MB0831D0055435446BBC2C172FD9DA0 () SN1PR09MB0831 ! namprd09 ! prod ! outlook ! com
[Download RAW message or body]
Dear Ettus x310 FPGA expert-
I am doing some custom fpga development in the radio core of the x310 design.
Vivado is telling me that I am failing timing in the radio_clk_2x domain. Since I am \
only working inside radio core I am not touching the radio_clk_2x world but \
experience has shown me that putting pressure on one part of the design can cause a \
problem somewhere else. Unfortunately this error does not help me narrow it down. \
Have you seen this violation before? Maybe extra registers on my stuff heading toward \
the DAC would help? My custom logic is inserted between the new_tx_control and the \
duc_chain_x300.
Thanks
Jeff Long
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) : -0.008ns (required time - arrival time)
Source: gen_db0/rising_edge_reg/C
(rising edge-triggered cell FDRE clocked by radio_clk_2x \
{rise@-0.312ns fall@0.938ns period=2.500ns}) Destination: \
gen_db0/gen_pins[3].oddr/D2
(rising edge-triggered cell ODDR clocked by radio_clk_2x \
{rise@-0.312ns fall@0.938ns period=2.500ns}) Path Group: radio_clk_2x
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (radio_clk_2x rise@2.187ns - radio_clk_2x \
rise@-0.312ns) Data Path Delay: 1.716ns (logic 0.270ns (15.733%) route \
1.446ns (84.267%)) Logic Levels: 1 (LUT3=1)
Clock Path Skew: -0.174ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -0.271ns = ( 1.916 - 2.187 )
Source Clock Delay (SCD): -0.701ns = ( -1.013 - -0.312 )
Clock Pessimism Removal (CPR): -0.603ns
Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.081ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist \
Resource(s)
------------------------------------------------------------------- \
------------------- (clock radio_clk_2x rise edge)
-0.312 -0.312 r
clock source latency 1.595 1.283
AF22 0.000 1.283 r FPGA_CLK_p \
(IN)
net (fo=0) 0.000 1.283 \
radio_clk_gen/inst/CLK_IN1_p AF22 IBUFDS (Prop_ibufds_I_O) 0.754 \
2.037 r radio_clk_gen/inst/clkin1_ibufgds/O
net (fo=1, routed) 1.081 3.118 \
radio_clk_gen/inst/CLK_IN1_radio_clk_gen MMCME2_ADV_X0Y0 MMCME2_ADV \
(Prop_mmcme2_adv_CLKIN1_CLKOUT1)
-8.315 -5.197 r \
radio_clk_gen/inst/mmcm_adv_inst/CLKOUT1
net (fo=1, routed) 2.554 -2.643 \
radio_clk_gen/inst/CLK_OUT2_radio_clk_gen BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) \
0.093 -2.550 r radio_clk_gen/inst/clkout2_buf/O
net (fo=88, routed) 1.537 -1.013 gen_db0/CLK
SLICE_X9Y138 FDRE r \
gen_db0/rising_edge_reg/C
------------------------------------------------------------------- \
------------------- SLICE_X9Y138 FDRE (Prop_fdre_C_Q) 0.223 \
-0.790 r gen_db0/rising_edge_reg/Q
net (fo=18, routed) 0.407 -0.383 \
gen_db0/rising_edge SLICE_X10Y134 LUT3 (Prop_lut3_I2_O) 0.047 \
-0.336 r gen_db0/gen_pins[3].oddr_i_2/O
net (fo=1, routed) 1.039 0.703 \
gen_db0/i_and_q_2x[3] OLOGIC_X0Y164 ODDR \
r gen_db0/gen_pins[3].oddr/D2
------------------------------------------------------------------- \
-------------------
(clock radio_clk_2x rise edge)
2.187 2.187 r
clock source latency 1.495 3.682
AF22 0.000 3.682 r FPGA_CLK_p \
(IN)
net (fo=0) 0.000 3.682 \
radio_clk_gen/inst/CLK_IN1_p AF22 IBUFDS (Prop_ibufds_I_O) 0.678 \
4.360 r radio_clk_gen/inst/clkin1_ibufgds/O
net (fo=1, routed) 0.986 5.346 \
radio_clk_gen/inst/CLK_IN1_radio_clk_gen MMCME2_ADV_X0Y0 MMCME2_ADV \
(Prop_mmcme2_adv_CLKIN1_CLKOUT1)
-7.280 -1.934 r \
radio_clk_gen/inst/mmcm_adv_inst/CLKOUT1
net (fo=1, routed) 2.417 0.483 \
radio_clk_gen/inst/CLK_OUT2_radio_clk_gen BUFGCTRL_X0Y4 BUFG (Prop_bufg_I_O) \
0.083 0.566 r radio_clk_gen/inst/clkout2_buf/O
net (fo=88, routed) 1.350 1.916 gen_db0/CLK
OLOGIC_X0Y164 ODDR r \
gen_db0/gen_pins[3].oddr/C clock pessimism -0.603 1.313
clock uncertainty -0.054 1.259
OLOGIC_X0Y164 ODDR (Setup_oddr_C_D2) -0.564 0.695 \
gen_db0/gen_pins[3].oddr
-------------------------------------------------------------------
required time 0.695
arrival time -0.703
-------------------------------------------------------------------
slack -0.008
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<p class="MsoNormal">Dear Ettus x310 FPGA expert-<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I am doing some custom fpga development in the radio core of the \
x310 design. <o:p></o:p></p>
<p class="MsoNormal">Vivado is telling me that I am failing timing in the \
radio_clk_2x domain. Since I am only working inside radio core I am not touching the \
radio_clk_2x world but experience has shown me that putting pressure on one part of \
the design can cause a problem somewhere else. Unfortunately this error does not \
help me narrow it down. Have you seen this violation before? Maybe extra registers on \
my stuff heading toward the DAC would help? My custom logic is inserted between the \
new_tx_control and the duc_chain_x300.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks<o:p></o:p></p>
<p class="MsoNormal">Jeff Long<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Max Delay Paths<o:p></o:p></p>
<p class="MsoNormal">--------------------------------------------------------------------------------------<o:p></o:p></p>
<p class="MsoNormal">Slack (VIOLATED) : \
-0.008ns (required time - arrival time)<o:p></o:p></p> <p \
class="MsoNormal"> \
Source: \
gen_db0/rising_edge_reg/C<o:p></o:p></p> <p \
class="MsoNormal"> &n \
bsp; \
(rising edge-triggered cell FDRE clocked by radio_clk_2x {rise@-0.312ns \
fall@0.938ns period=2.500ns})<o:p></o:p></p> <p class="MsoNormal"> \
Destination: \
gen_db0/gen_pins[3].oddr/D2<o:p></o:p></p> <p \
class="MsoNormal"> &n \
bsp; \
(rising edge-triggered cell ODDR clocked by radio_clk_2x {rise@-0.312ns \
fall@0.938ns period=2.500ns})<o:p></o:p></p> <p class="MsoNormal"> Path \
Group: \
radio_clk_2x<o:p></o:p></p> <p class="MsoNormal"> Path \
Type: \
Setup (Max at Slow Process Corner)<o:p></o:p></p> <p class="MsoNormal"> \
Requirement: \
2.500ns (radio_clk_2x rise@2.187ns - radio_clk_2x rise@-0.312ns)<o:p></o:p></p> \
<p class="MsoNormal"> Data Path \
Delay: 1.716ns (logic 0.270ns \
(15.733%) route 1.446ns (84.267%))<o:p></o:p></p> <p class="MsoNormal"> \
Logic Levels: 1 \
(LUT3=1)<o:p></o:p></p> <p class="MsoNormal"> Clock Path \
Skew: -0.174ns (DCD - SCD + \
CPR)<o:p></o:p></p> <p class="MsoNormal"> Destination Clock Delay \
(DCD): -0.271ns = ( 1.916 - 2.187 ) <o:p></o:p></p>
<p class="MsoNormal"> Source Clock \
Delay (SCD): -0.701ns = ( -1.013 - \
-0.312 ) <o:p></o:p></p>
<p class="MsoNormal"> Clock Pessimism Removal \
(CPR): -0.603ns<o:p></o:p></p> <p class="MsoNormal"> Clock \
Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 \
+ PE<o:p></o:p></p> <p class="MsoNormal"> Total System \
Jitter (TSJ): 0.071ns<o:p></o:p></p> <p \
class="MsoNormal"> Discrete \
Jitter (DJ): \
0.081ns<o:p></o:p></p> <p class="MsoNormal"> Phase \
Error \
(PE): 0.000ns<o:p></o:p></p> <p \
class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal"> \
Location \
Delay type \
Incr(ns) Path(ns) Netlist Resource(s)<o:p></o:p></p> <p \
class="MsoNormal"> \
------------------------------------------------------------------- \
-------------------<o:p></o:p></p> <p \
class="MsoNormal"> \
(clock radio_clk_2x rise edge)<o:p></o:p></p> <p \
class="MsoNormal"> &n \
bsp; &nbs \
p; \
-0.312 -0.312 r <o:p></o:p></p>
<p class="MsoNormal">   \
; clock \
source latency \
1.595 1.283 <o:p></o:p></p>
<p class="MsoNormal"> AF22 & \
nbsp; &nb \
sp; \
0.000 1.283 r FPGA_CLK_p (IN)<o:p></o:p></p> <p \
class="MsoNormal"> \
net (fo=0) \
0.000 1.283 \
radio_clk_gen/inst/CLK_IN1_p<o:p></o:p></p> <p class="MsoNormal"> \
AF22 \
IBUFDS (Prop_ibufds_I_O) 0.754 2.037 \
r radio_clk_gen/inst/clkin1_ibufgds/O<o:p></o:p></p> <p \
class="MsoNormal"> \
net (fo=1, routed) \
1.081 3.118 \
radio_clk_gen/inst/CLK_IN1_radio_clk_gen<o:p></o:p></p> <p \
class="MsoNormal"> MMCME2_ADV_X0Y0 \
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)<o:p></o:p></p> <p \
class="MsoNormal"> &n \
bsp; &nbs \
p; \
-8.315 -5.197 r \
radio_clk_gen/inst/mmcm_adv_inst/CLKOUT1<o:p></o:p></p> <p \
class="MsoNormal"> \
net (fo=1, routed) \
2.554 -2.643 \
radio_clk_gen/inst/CLK_OUT2_radio_clk_gen<o:p></o:p></p> <p \
class="MsoNormal"> \
BUFGCTRL_X0Y4 BUFG \
(Prop_bufg_I_O) \
0.093 -2.550 r \
radio_clk_gen/inst/clkout2_buf/O<o:p></o:p></p> <p \
class="MsoNormal"> \
net (fo=88, routed) \
1.537 -1.013 gen_db0/CLK<o:p></o:p></p> <p \
class="MsoNormal"> \
SLICE_X9Y138 \
FDRE \
&n \
bsp; r \
gen_db0/rising_edge_reg/C<o:p></o:p></p> <p class="MsoNormal"> \
------------------------------------------------------------------- \
-------------------<o:p></o:p></p> <p class="MsoNormal"> \
SLICE_X9Y138 FDRE \
(Prop_fdre_C_Q) \
0.223 -0.790 r gen_db0/rising_edge_reg/Q<o:p></o:p></p> <p \
class="MsoNormal"> \
net \
(fo=18, routed) \
0.407 -0.383 gen_db0/rising_edge<o:p></o:p></p> \
<p class="MsoNormal"> \
SLICE_X10Y134 LUT3 \
(Prop_lut3_I2_O) 0.047 \
-0.336 r gen_db0/gen_pins[3].oddr_i_2/O<o:p></o:p></p> <p \
class="MsoNormal"> \
net (fo=1, routed) \
1.039 0.703 \
gen_db0/i_and_q_2x[3]<o:p></o:p></p> <p class="MsoNormal"> \
OLOGIC_X0Y164 \
ODDR &nbs \
p; \
r gen_db0/gen_pins[3].oddr/D2<o:p></o:p></p> <p class="MsoNormal"> \
------------------------------------------------------------------- \
-------------------<o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"> \
(clock radio_clk_2x rise edge)<o:p></o:p></p> <p \
class="MsoNormal"> &n \
bsp; &nbs \
p; \
2.187 2.187 r <o:p></o:p></p>
<p class="MsoNormal">   \
; clock \
source latency \
1.495 3.682 <o:p></o:p></p>
<p class="MsoNormal"> AF22 & \
nbsp; &nb \
sp; \
0.000 3.682 r FPGA_CLK_p \
(IN)<o:p></o:p></p> <p \
class="MsoNormal"> \
net (fo=0) \
0.000 3.682 \
radio_clk_gen/inst/CLK_IN1_p<o:p></o:p></p> <p class="MsoNormal"> \
AF22 \
IBUFDS (Prop_ibufds_I_O) 0.678 4.360 \
r radio_clk_gen/inst/clkin1_ibufgds/O<o:p></o:p></p> <p \
class="MsoNormal"> \
net \
(fo=1, routed) \
0.986 5.346 \
radio_clk_gen/inst/CLK_IN1_radio_clk_gen<o:p></o:p></p> <p \
class="MsoNormal"> MMCME2_ADV_X0Y0 \
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)<o:p></o:p></p> <p \
class="MsoNormal"> &n \
bsp; &nbs \
p; \
-7.280 -1.934 r \
radio_clk_gen/inst/mmcm_adv_inst/CLKOUT1<o:p></o:p></p> <p \
class="MsoNormal"> \
net (fo=1, routed) \
2.417 0.483 \
radio_clk_gen/inst/CLK_OUT2_radio_clk_gen<o:p></o:p></p> <p \
class="MsoNormal"> \
BUFGCTRL_X0Y4 BUFG \
(Prop_bufg_I_O) \
0.083 0.566 r \
radio_clk_gen/inst/clkout2_buf/O<o:p></o:p></p> <p class="MsoNormal"> \
net \
(fo=88, routed) \
1.350 1.916 gen_db0/CLK<o:p></o:p></p> <p \
class="MsoNormal"> \
OLOGIC_X0Y164 \
ODDR &nbs \
p; \
r gen_db0/gen_pins[3].oddr/C<o:p></o:p></p> <p \
class="MsoNormal"> \
clock pessimism \
-0.603 1.313 <o:p></o:p></p>
<p class="MsoNormal">   \
; clock \
uncertainty \
-0.054 1.259 <o:p></o:p></p>
<p class="MsoNormal"> OLOGIC_X0Y164 \
ODDR (Setup_oddr_C_D2) -0.564 \
0.695 gen_db0/gen_pins[3].oddr<o:p></o:p></p> <p \
class="MsoNormal"> \
-------------------------------------------------------------------<o:p></o:p></p> <p \
class="MsoNormal"> \
required \
time \
0.695 <o:p></o:p></p>
<p class="MsoNormal">   \
; arrival \
time \
-0.703 <o:p></o:p></p>
<p class="MsoNormal"> -------------------------------------------------------------------<o:p></o:p></p>
<p class="MsoNormal"> \
slack \
-0.008
<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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