'[USRP-users] RFNoC module test bench'

[prev in list] [next in list] [prev in thread] [next in thread] 

List:       usrp-users
Subject:    [USRP-users] RFNoC module test bench
From:       Eugene Chai via USRP-users <usrp-users () lists ! ettus ! com>
Date:       2015-10-29 22:28:58
Message-ID: B8ECFA22-095B-40FA-A996-962F295FC7BD () nec-labs ! com
[Download RAW message or body]

Hello,

I am writing a new CE using the RFNoC framework, but I've encountered the following \
error message when I run "make xsim" inside the testbench folder.  The same error \
occurs when I run the test bench from "noc_block_moving_avg_tb", and I've copied the \
error output here.  

Does anybody know how I can resolve this?

==================================================
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto \
703babd3987d4efea4e5032ef5bc521b --debug all --relax --mt 8 --include \
../../../../../../../sim/general --include ../../../../../../../sim/rfnoc -d \
SIM_RUNTIME_US=1000 -d \
WORKING_DIR=/mnt/hdd0/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_moving_avg_tb -L \
xil_defaultlib -L fifo_generator_v12_0 -L xbip_utils_v3_0 -L axi_utils_v2_0 -L \
xbip_pipe_v3_0 -L xbip_dsp48_wrapper_v3_0 -L xbip_dsp48_addsub_v3_0 -L \
xbip_bram18k_v3_0 -L mult_gen_v12_0 -L floating_point_v7_0 -L xbip_dsp48_mult_v3_0 -L \
xbip_dsp48_multadd_v3_0 -L div_gen_v5_1 -L unisims_ver -L unimacro_ver -L secureip \
--snapshot noc_block_moving_avg_tb_behav xil_defaultlib.noc_block_moving_avg_tb \
xil_defaultlib.glbl -log elaborate.log  Using 8 slave threads.
Starting static elaboration
ERROR: [VRFC 10-900] incompatible complex type assignment [sim_axis_lib.sv:30]
WARNING: [VRFC 10-727] function new has no return value assignment \
                [sim_axis_lib.sv:29]
ERROR: [VRFC 10-900] incompatible complex type assignment [sim_axis_lib.sv:105]
WARNING: [VRFC 10-727] function new has no return value assignment \
                [sim_axis_lib.sv:104]
ERROR: [VRFC 10-900] incompatible complex type assignment [sim_axis_lib.sv:170]
ERROR: [VRFC 10-900] incompatible complex type assignment [sim_axis_lib.sv:171]
WARNING: [VRFC 10-727] function new has no return value assignment \
                [sim_axis_lib.sv:169]
ERROR: [VRFC 10-900] incompatible complex type assignment [sim_cvita_lib.sv:69]
WARNING: [VRFC 10-727] function new has no return value assignment \
                [sim_cvita_lib.sv:68]
ERROR: [VRFC 10-900] incompatible complex type assignment [sim_cvita_lib.sv:150]
WARNING: [VRFC 10-727] function new has no return value assignment \
                [sim_cvita_lib.sv:149]
ERROR: [VRFC 10-900] incompatible complex type assignment [sim_cvita_lib.sv:191]
ERROR: [VRFC 10-900] incompatible complex type assignment [sim_cvita_lib.sv:196]
ERROR: [VRFC 10-900] incompatible complex type assignment [sim_cvita_lib.sv:237]
ERROR: [VRFC 10-900] incompatible complex type assignment [sim_cvita_lib.sv:238]
WARNING: [VRFC 10-727] function new has no return value assignment \
                [sim_cvita_lib.sv:236]
WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 3 for port \
                rb_addr \
                [/mnt/hdd0/src/uhd/fpga-src/usrp3/lib/control/axi_crossbar_intf.sv:80]

WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 64 for \
                port rb_data \
                [/mnt/hdd0/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_export_io.sv:65]

WARNING: [VRFC 10-278] actual bit length 8 differs from formal bit length 32 for port \
                out [/mnt/hdd0/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_export_io.sv:122]

WARNING: [VRFC 10-597] element index -1 into num_read_words_dc is out of bounds \
[/mnt/hdd0/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_moving_avg_tb/build-ip/xc7k410tf \
fg900-2/fifo_short_2clk/fifo_generator_v12_0/simulation/fifo_generator_vlog_beh.v:5194]

WARNING: [VRFC 10-597] element index -1 into num_write_words_dc is out of bounds \
[/mnt/hdd0/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_moving_avg_tb/build-ip/xc7k410tf \
fg900-2/fifo_short_2clk/fifo_generator_v12_0/simulation/fifo_generator_vlog_beh.v:5244]

ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in \
                library work failed.
INFO: [USF-XSim-99] Step results log \
file:'/mnt/hdd0/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_moving_avg_tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log'

ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl \
console output or '/mnt/hdd0/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_moving_avg_tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log' \
                file for more information.
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak \
= 910.949 ; gain = 5.000 ; free physical = 12259 ; free virtual = 251673 # if [string \
equal $vivado_mode "batch"] { #     puts "BUILDER: Closing project"
#     close_project
# } else {
#     puts "BUILDER: In GUI mode. Leaving project open."
# }
BUILDER: Closing project

Thanks,
Eugene

_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

[prev in list] [next in list] [prev in thread] [next in thread] 