On 03/01/2011 05:48 AM, digital design wrote:
> Good day!
> I'm creating HDL IP CORE (for using in FPGA) for theora encoder (now
> only I-frames).
> I don't undestand one moment. Now i develop such stages:
> 1. From RBG(byer) to YCbCr converter
> 2. DCT processing (8x8 pixels blocks)
> 3. Quantizator of DCT coeff.
> 4. Zig-Zag of quantized DCT coeff.
> and now i have uresolved last stage of compression - how i must send 8x8
> blocks to huffman compressor? I don't understand ordering.
> I must send all DC coeff (Y, than Cb,Cr), after all AC-0 (Y, than Cb,Cr)
> .... after all AC-63 (Y, than Cb,Cr)? And put huffman compression result
> to buffer memory like this:
> huffman compression products of all DC coeff (Y, than Cb,Cr), after all
> AC-0 (Y, than Cb,Cr) .... after all AC-63 (Y, than Cb,Cr)?
>
> Please explain me this moment. I need your help.

That's most of it. But did you differentially encode the DC 
coefficients? And did you Huffman-code in a Hilbert order? Those are 2 
steps notably absent from your description.

-- 
     -Mike Melanson
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