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List: rockbox-cvs
Subject: Xduoo X3 - Grey scale lib update
From: rockbox-gerrit-noreply--- via rockbox-cvs <rockbox-cvs () cool ! haxx ! se>
Date: 2020-08-27 14:33:26
Message-ID: 202008271433.07REXQiR2871376 () stuffed ! shaftnet ! org
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commit 5fb4c74bfb16f2dcf1249b04c491526ca89b1fad
Author: William Wilgus <wilgus.william@gmail.com>
Date: Thu Aug 27 10:06:19 2020 -0400
Xduoo X3 - Grey scale lib update
greylib on the xduoo x3 now matches the rest of the 1bit targets
Change-Id: I2685869da6734404356552cc9f4ed5f59ebd6650
diff --git a/firmware/export/jz4760b.h b/firmware/export/jz4760b.h
index c35e26767f..be1e4f3aea 100644
--- a/firmware/export/jz4760b.h
+++ b/firmware/export/jz4760b.h
@@ -242,31 +242,31 @@
#ifndef __MIPS_ASSEMBLER
//n = 0,1,2,3,4,5 (PORTA, PORTB, PORTC, PORTD, PORTE, PORTF)
-#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN(n))
-#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT(n))
-#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS(n))
-#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC(n))
-#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM(n))
-#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS(n))
-#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC(n))
-#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE(n))
-#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES(n))
-#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC(n))
-#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN(n))
-#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS(n))
-#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC(n))
-#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL(n))
-#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS(n))
-#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC(n))
-#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR(n))
-#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS(n))
-#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC(n))
-#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG(n))
-#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS(n))
-#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC(n))
-#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG(n))
-#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC(n))
-#define REG_GPIO_PXDS0(n) REG32(GPIO_PXDS0(n))
+#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN(n)) /* PIN Level Register */
+#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT(n)) /* Port Data Register */
+#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS(n)) /* Port Data Set Register */
+#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC(n)) /* Port Data Clear Register */
+#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM(n)) /* Interrupt Mask Register */
+#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS(n)) /* Interrupt Mask Set Reg */
+#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC(n)) /* Interrupt Mask Clear Reg */
+#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE(n)) /* Pull Enable Register */
+#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES(n)) /* Pull Enable Set Register */
+#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC(n)) /* Pull Enable Clear Register */
+#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN(n)) /* Function Register */
+#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS(n)) /* Function Set Register */
+#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC(n)) /* Function Clear Register */
+#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL(n)) /* Select Register */
+#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS(n)) /* Select Set Register */
+#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC(n)) /* Select Clear Register */
+#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR(n)) /* Direction Register */
+#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS(n)) /* Direction Set Register */
+#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC(n)) /* Direction Clear Register */
+#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG(n)) /* Trigger Register */
+#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS(n)) /* Trigger Set Register */
+#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC(n)) /* Trigger Clear Register */
+#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG(n)) /* Port Flag Register */
+#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC(n)) /* Port Flag clear Register */
+#define REG_GPIO_PXDS0(n) REG32(GPIO_PXDS0(n)) /* Port Drive Strength*/
#define REG_GPIO_PXDS0S(n) REG32(GPIO_PXDS0S(n))
#define REG_GPIO_PXDS0C(n) REG32(GPIO_PXDS0C(n))
#define REG_GPIO_PXDS1(n) REG32(GPIO_PXDS1(n))
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c \
b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c index \
89251b727d..ea29ce266d 100644
--- a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c
+++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c
@@ -301,28 +301,29 @@ void lcd_blit_mono(const unsigned char *data, int x, int by, \
int width, void lcd_grey_data(unsigned char *values, unsigned char *phases, int \
count) ICODE_ATTR; void lcd_grey_data(unsigned char *values, unsigned char *phases, \
int count) {
- unsigned char a, b, c, d;
+ unsigned long ltmp;
+ unsigned long *lval = (unsigned long *)values;
+ unsigned long *lpha = (unsigned long *)phases;
+ const unsigned long mask = 0x80808080;
- __gpio_set_pin(PIN_LCD_DC);
while(count--)
{
- c = 0;
- d = 8;
- while(d--)
- {
- a = *phases;
- b = *values++;
- b += a & ~0x80;
- *phases++ = b;
- c <<= 1;
- c |= a >> 7;
- }
- REG_GPIO_PXDATC(2) = 0x000030FC;
- REG_GPIO_PXDATS(2) = ((c & 0xC0) << 6) | ((c & 0x3F) << 2);
- __gpio_clear_pin(PIN_LCD_WR);
- bitdelay();
- __gpio_set_pin(PIN_LCD_WR);
- bitdelay();
+ /* calculate disp data from phase we only use the last byte (8bits) */
+ ltmp = mask & lpha[0]; // ltmp= 3.......2.......1.......0.......
+ ltmp |= (mask & lpha[1]) >> 4; // ltmp= 7.......6.......5.......4.......
+ /* phase0 | phase1 >> 4 */ // ltmp= 3...7...2...6...1...5...0...4...
+ ltmp |= ltmp >> 9; // ltmp= 3...7...23..67..12..56..01..45..
+ ltmp |= ltmp >> 9; // ltmp= 3...7...23..67..123.567.012.456.
+ ltmp |= ltmp >> 9; // ltmp= 3...7...23..67..123.567.01234567
+
+ /* update the phases */
+ lpha[0] = lval[0] + (lpha[0] & ~mask);
+ lpha[1] = lval[1] + (lpha[1] & ~mask);
+
+ lcd_write_data((const fb_data*) <mp, 1);
+
+ lpha+=2;
+ lval+=2;
}
}
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