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List:       qemu-riscv
Subject:    [PATCH] qemu: riscv: rvv: fix vmv.v.x for RV32, el64, vl == vl_max
From:       Robert Bu <robert.bu () gmail ! com>
Date:       2022-05-31 6:45:09
Message-ID: CAMSqtnyQ3On5SA41kmWa7Eb1S-zvZfET9n8-fBPSV06ZrFRxYg () mail ! gmail ! com
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["0001-qemu-riscv-rvv-fix-vmv.v.x-for-RV32-el64-vl-vl_max.patch" (text/plain)]

From 6198f587f14f8773343dded83b6c0edfd7dbf88e Mon Sep 17 00:00:00 2001
From: Robert Bu <robert_bu@gmail.com>
Date: Wed, 18 May 2022 09:08:52 +0800
Subject: [PATCH] qemu: riscv: rvv: fix vmv.v.x for RV32, el64, vl == vl_max

Signed-off-by: Robert Bu <robert.bu@gmail.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 391c61fe93..6b27d8e91e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2097,8 +2097,16 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
         s1 = get_gpr(s, a->rs1, EXT_SIGN);
 
         if (s->vl_eq_vlmax) {
-            tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
-                                MAXSZ(s), MAXSZ(s), s1);
+            if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
+                TCGv_i64 s1_i64 = tcg_temp_new_i64();
+                tcg_gen_ext_tl_i64(s1_i64, s1);
+                tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+                                     MAXSZ(s), MAXSZ(s), s1_i64);
+                tcg_temp_free_i64(s1_i64);
+            } else {
+                tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
+                                    MAXSZ(s), MAXSZ(s), s1);
+            }
         } else {
             TCGv_i32 desc;
             TCGv_i64 s1_i64 = tcg_temp_new_i64();
-- 
2.31.1



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