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List:       qemu-riscv
Subject:    Re: [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support
From:       Leif Lindholm <leif () nuviainc ! com>
Date:       2020-08-30 23:35:52
Message-ID: 20200830233552.GG20124 () vanye
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On Mon, Aug 31, 2020 at 06:15:52 +0800, Bin Meng wrote:
> Hi Leif,
> 
> > > The following perepherals are emulated:
> > > - SiFive CLINT
> > > - SiFive PLIC
> > > - PolarFire SoC Multi-Mode UART
> > > - SiFive PDMA
> > > - Cadence eMMC/SDHCI controller
> > > - Cadence Gigabit Ethernet MAC
> > >
> > > The BIOS image used by this machine is hss.bin, aka Hart Software
> > > Services, which can be built from:
> > > https://github.com/polarfire-soc/hart-software-services
> >
> > Are there any version requirements, or additional qemu patches, that
> > need to be taken into account. Should I expect to see output on stdio?
> 
> Thanks for trying!
> 
> Did you apply the patch to skip the DDR memory initialization
> mentioned in this page?
> https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit

I did, but in honesty only after I sent the previous email :)
(Since it made no difference, I didn't bother following up.)

> > I tried to build hss 3faaaaf8ce0d, using
> > https://github.com/riscv/riscv-gnu-toolchain (7f1f4ab5b0e0), which
> > ends up being a gcc 10.1. That caused me to raise
> > https://github.com/polarfire-soc/hart-software-services/issues/2.
> 
> Yes, GCC 10 does not build is a known issue. Currently I am using GCC
> 9 to build HSS.

Right, I can confirm that with commit 93f82dc18e1d riscv-gnu-toolchain
(the last before changing to gcc 10.1), I generate a 9.2.0 gcc that
builds a hss.bin that boots successfully with the minimal command line

qemu-system-riscv64 -M microchip-icicle-kit -smp 5 -bios hss.bin \
  -display none -serial stdio

Thanks!

(I haven't looked any further than the hss.bin yet, but I'm now
unblocked to do so.)

Best Regards,

Leif


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