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List:       qemu-riscv
Subject:    Re: [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction
From:       Richard Henderson <richard.henderson () linaro ! org>
Date:       2020-07-31 16:45:45
Message-ID: fbb66f8c-62af-97aa-48bb-1a26d5baeb29 () linaro ! org
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On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
>  # Vector ordered and unordered reduction sum
> -vfredsum_vs     0000-1 . ..... ..... 001 ..... 1010111 @r_vm
> +vfredsum_vs     000001 . ..... ..... 001 ..... 1010111 @r_vm
> +vfredosum_vs    000011 . ..... ..... 001 ..... 1010111 @r_vm

"The vfredosum instruction is a valid implementation of the vfredsum instruction."

Which is exactly what we're doing here.

Why should we treat them differently?  There is no parallelism that we can
exploit in tcg, unlike in hardware.


r~


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