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List:       qemu-riscv
Subject:    Re: [RFC v2 49/76] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
From:       Richard Henderson <richard.henderson () linaro ! org>
Date:       2020-07-30 21:19:26
Message-ID: 3d2e0fb3-f616-7e4f-efd5-0f607644d5eb () linaro ! org
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On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> Add the following instructions:
> 
> * vqmaccu.vv
> * vqmaccu.vx
> * vqmacc.vv
> * vqmacc.vx
> * vqmaccsu.vv
> * vqmaccsu.vx
> * vqmaccus.vx
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/helper.h                   |  15 ++++
>  target/riscv/insn32.decode              |   7 ++
>  target/riscv/insn_trans/trans_rvv.inc.c | 101 ++++++++++++++++++++++++
>  target/riscv/vector_helper.c            |  40 ++++++++++
>  4 files changed, 163 insertions(+)

Looks ok.  I presume you'll add the Zvqmac test now that's in the draft?


r~


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