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List:       qemu-riscv
Subject:    Re: [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended
From:       Richard Henderson <richard.henderson () linaro ! org>
Date:       2020-07-30 13:43:18
Message-ID: bcc93273-4e1f-9604-46f2-0b682a3c9184 () linaro ! org
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On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> For some vector instructions (e.g. vmv.s.x), the element is loaded with
> sign-extended.
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/insn_trans/trans_rvv.inc.c | 26 ++++++++++++++++++-------
>  1 file changed, 19 insertions(+), 7 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


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