[prev in list] [next in list] [prev in thread] [next in thread] 

List:       qemu-riscv
Subject:    Re: [Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti
From:       Richard Henderson <richard.henderson () linaro ! org>
Date:       2019-04-25 16:50:41
Message-ID: 357d260b-4baf-aea8-c332-f77ce2a3e9b2 () linaro ! org
[Download RAW message or body]

On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>  # *** RV64C Standard Extension (Quadrant 2) ***
>> -c_slli            000 .  .....  ..... 10 @c_shift2
>> +slli              000 .  .....  ..... 10 @c_shift2
> 
> This is another one where rd=0 is illegal in the compressed ISA, but again we
> don't appear to handle these correctly before the cleanups.

I see "HINT, rd=0" in the 2.2 documentation for this case.


r~


[prev in list] [next in list] [prev in thread] [next in thread]