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List:       qemu-riscv
Subject:    [Qemu-riscv] [PATCH v1 3/8] target/riscv: Improve the scause logic
From:       Alistair Francis <Alistair.Francis () wdc ! com>
Date:       2019-04-20 2:27:02
Message-ID: d32a88fc0506a7bc1cae31c2fdf1448d2469e9d3.1555727081.git.alistair.francis () wdc ! com
[Download RAW message or body]

No functional change, just making the code easier to read.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 582d58aad9..e7d9dd95cc 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -525,7 +525,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
         s = set_field(s, MSTATUS_SPP, env->priv);
         s = set_field(s, MSTATUS_SIE, 0);
         env->mstatus = s;
-        env->scause = cause | ~(((target_ulong)-1) >> async);
+        env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
         env->sepc = env->pc;
         env->sbadaddr = tval;
         env->pc = (env->stvec >> 2 << 2) +
-- 
2.21.0


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