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List:       qemu-ppc
Subject:    Re: [RFC PATCH 1/7] target/ppc: Implement xxm[tf]acc and xxsetaccz
From:       Richard Henderson <richard.henderson () linaro ! org>
Date:       2022-04-26 22:59:44
Message-ID: 54854d2c-aab2-0f85-4099-65dd1621b940 () linaro ! org
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On 4/26/22 05:50, Lucas Mateus Castro(alqotel) wrote:
> From: "Lucas Mateus Castro (alqotel)"<lucas.araujo@eldorado.org.br>
> 
> Implement the following PowerISA v3.1 instructions:
> xxmfacc: VSX Move From Accumulator
> xxmtacc: VSX Move To Accumulator
> xxsetaccz: VSX Set Accumulator to Zero
> 
> The PowerISA 3.1 mentions that for the current version of the
> architecture, "the hardware implementation provides the effect of ACC[i]
> and VSRs 4*i to 4*i + 3 logically containing the same data" and "The
> Accumulators introduce no new logical state at this time" (page 501).
> For now it seems unnecessary to create new structures, so this patch
> just uses ACC[i] as VSRs 4*i to 4*i+3 and therefore move to and from
> accumulators are no-ops.
> 
> Signed-off-by: Lucas Mateus Castro (alqotel)<lucas.araujo@eldorado.org.br>
> ---
>   target/ppc/insn32.decode            |  9 ++++++++
>   target/ppc/translate/vsx-impl.c.inc | 36 +++++++++++++++++++++++++++++
>   2 files changed, 45 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


> +    TCGv_i64 zero = tcg_constant_i64(0);
> +    for (i = 0; i < 4; i++) {
> +        set_cpu_vsr(a->ra * 4 + i, zero, false);
> +        set_cpu_vsr(a->ra * 4 + i, zero, true);
> +    }

or

   tcg_gen_gvec_dup_imm(MO_64, acc_full_offset(a->ra), 64, 64, 0);


r~

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