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List: qemu-ppc
Subject: Re: [PATCH] target/ppc: Remove 440x4 CPU
From: Cédric_Le_Goater <clg () kaod ! org>
Date: 2022-01-31 14:41:09
Message-ID: ecce8be7-5294-e1d5-27a9-a790fe447889 () kaod ! org
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On 1/28/22 23:16, Fabiano Rosas wrote:
> This CPU was partially removed due to lack of support in 2017 by commit
> aef7796057 ("ppc: remove non implemented cpu models").
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/cpu_init.c | 83 -------------------------------------------
> 1 file changed, 83 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index e30e86fe9d..f4a4f39419 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2777,89 +2777,6 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
> POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
> }
>
> -static void init_proc_440x4(CPUPPCState *env)
> -{
> - /* Time base */
> - register_tbl(env);
> - register_BookE_sprs(env, 0x000000000000FFFFULL);
> - register_440_sprs(env);
> - register_usprgh_sprs(env);
> - /* Processor identification */
> - spr_register(env, SPR_BOOKE_PIR, "PIR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_pir,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_BOOKE_IAC3, "IAC3",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_BOOKE_IAC4, "IAC4",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_BOOKE_DVC1, "DVC1",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_BOOKE_DVC2, "DVC2",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* Memory management */
> -#if !defined(CONFIG_USER_ONLY)
> - env->nb_tlb = 64;
> - env->nb_ways = 1;
> - env->id_tlbs = 0;
> - env->tlb_type = TLB_EMB;
> -#endif
> - init_excp_BookE(env);
> - env->dcache_line_size = 32;
> - env->icache_line_size = 32;
> - /* XXX: TODO: allocate internal IRQ controller */
> -
> - SET_FIT_PERIOD(12, 16, 20, 24);
> - SET_WDT_PERIOD(20, 24, 28, 32);
> -}
> -
> -POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> -
> - dc->desc = "PowerPC 440x4";
> - pcc->init_proc = init_proc_440x4;
> - pcc->check_pow = check_pow_nocheck;
> - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
> - PPC_DCR | PPC_WRTEE |
> - PPC_CACHE | PPC_CACHE_ICBI |
> - PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
> - PPC_MEM_TLBSYNC | PPC_MFTB |
> - PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
> - PPC_440_SPEC;
> - pcc->msr_mask = (1ull << MSR_POW) |
> - (1ull << MSR_CE) |
> - (1ull << MSR_EE) |
> - (1ull << MSR_PR) |
> - (1ull << MSR_FP) |
> - (1ull << MSR_ME) |
> - (1ull << MSR_FE0) |
> - (1ull << MSR_DWE) |
> - (1ull << MSR_DE) |
> - (1ull << MSR_FE1) |
> - (1ull << MSR_IR) |
> - (1ull << MSR_DR);
> - pcc->mmu_model = POWERPC_MMU_BOOKE;
> - pcc->excp_model = POWERPC_EXCP_BOOKE;
> - pcc->bus_model = PPC_FLAGS_INPUT_BookE;
> - pcc->bfd_mach = bfd_mach_ppc_403;
> - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
> - POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
> -}
> -
> static void init_proc_440x5(CPUPPCState *env)
> {
> /* Time base */
>
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