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List:       qemu-ppc
Subject:    Re: [Qemu-ppc] [0/48] target-ppc: MMU implementation cleanup for hash MMUs
From:       Alexander Graf <agraf () suse ! de>
Date:       2013-03-21 13:43:44
Message-ID: 3D4CBC2F-B4FC-4EA6-BCAE-645A09165CA6 () suse ! de
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On 12.03.2013, at 11:31, David Gibson wrote:

> This large patch series makes a serious overhaul of the MMU
> implementation for target-ppc.  Previously all the quite dissimilar
> PowerPC MMU variants attempted to use a more-or-less common code path,
> with dependencies on env->mmu_model scattered throughout.  The
> resulting confused code was not worth the handful of saved lines.
> 
> This series starts the transition to a new model, where the different
> MMU types are represented by appropriate QOM methods on the CPU
> object.  For now, only the main translation path - previously
> cpu_ppc_handle_mmu_fault() is made such a method, but more could be
> added in future.  For now, 32-bit and 64-bit hash page table based
> MMUs (the "classic" PPC MMUs) are given their own handle_mmu_fault
> functions - the remaining MMU types retain the old code for now, I'm
> hoping those more familiar with them will perform a similar conversion
> in future though.
> 
> There's plenty more cleanup that could be done.  As well as the
> obvious work to convert other MMU types, there's room for improvement
> in: handling of SDR1 and other SPRs, handling of segment registers,
> switching MMU code to user PowerPCCPU instead of CPUPPCState, remove
> the duplicate mmu_model in PowerpCCPUClass and CPUPPCState, removing
> remaining uses of mmu_model.  But if I tackled all those now, I might
> never get this series ready.

Thanks a lot, applied all to ppc-next :). With a few 32-bit host fixes. I'll only \
push it out once the other TCG breakage is solved, so that I can verify this actually \
works on 32-bit hosts (it fails there today, but very very likely not due to your \
patches)


Alex


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