From qemu-devel Mon Mar 25 09:48:57 2024 From: Helge Deller Date: Mon, 25 Mar 2024 09:48:57 +0000 To: qemu-devel Subject: Re: [PATCH 2/3] target/hppa: Optimize UADDCM with no condition Message-Id: <6ba279b9-51f1-4525-9227-b1601ba5eb7d () gmx ! de> X-MARC-Message: https://marc.info/?l=qemu-devel&m=171136002831315 On 3/25/24 04:04, Richard Henderson wrote: > With r1 as zero is by far the only usage of UADDCM, as the easiest > way to invert a register. The compiler does occasionally use the > addition step as well, and we can simplify that to avoid a temp > and write directly into the destination. > > Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Tested-by: Helge Deller Helge > --- > target/hppa/translate.c | 24 ++++++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) > > diff --git a/target/hppa/translate.c b/target/hppa/translate.c > index a3f425d861..3fc3e7754c 100644 > --- a/target/hppa/translate.c > +++ b/target/hppa/translate.c > @@ -2763,9 +2763,29 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_= cf_d *a, bool is_tc) > { > TCGv_i64 tcg_r1, tcg_r2, tmp; > > - if (a->cf) { > - nullify_over(ctx); > + if (a->cf =3D=3D 0) { > + tcg_r2 =3D load_gpr(ctx, a->r2); > + tmp =3D dest_gpr(ctx, a->t); > + > + if (a->r1 =3D=3D 0) { > + /* UADDCM r0,src,dst is the common idiom for dst =3D ~src. = */ > + tcg_gen_not_i64(tmp, tcg_r2); > + } else { > + /* > + * Recall that r1 - r2 =3D=3D r1 + ~r2 + 1. > + * Thus r1 + ~r2 =3D=3D r1 - r2 - 1, > + * which does not require an extra temporary. > + */ > + tcg_r1 =3D load_gpr(ctx, a->r1); > + tcg_gen_sub_i64(tmp, tcg_r1, tcg_r2); > + tcg_gen_subi_i64(tmp, tmp, 1); > + } > + save_gpr(ctx, a->t, tmp); > + cond_free(&ctx->null_cond); > + return true; > } > + > + nullify_over(ctx); > tcg_r1 =3D load_gpr(ctx, a->r1); > tcg_r2 =3D load_gpr(ctx, a->r2); > tmp =3D tcg_temp_new_i64();