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List:       qemu-devel
Subject:    Re: [Qemu-devel] [PATCH] [MIPS] Correctly identify multiple cpus
From:       Aurelien Jarno <aurelien () aurel32 ! net>
Date:       2010-07-31 15:17:13
Message-ID: 20100731151713.GJ20459 () volta ! aurel32 ! net
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On Sat, Jul 31, 2010 at 12:29:03PM +0200, Hervé Poussineau wrote:
> 
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> ---
>  target-mips/op_helper.c |    3 +--
>  target-mips/translate.c |    3 +--
>  2 files changed, 2 insertions(+), 4 deletions(-)

Thanks, applied.
 
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index a619b72..50c65bd 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -1359,8 +1359,7 @@ void helper_mtc0_cause (target_ulong arg1)
>  void helper_mtc0_ebase (target_ulong arg1)
>  {
>      /* vectored interrupts not implemented */
> -    /* Multi-CPU not implemented */
> -    env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
> +    env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
>  }
>  
>  void helper_mtc0_config0 (target_ulong arg1)
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 6c72dee..20b66a8 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -12679,8 +12679,7 @@ void cpu_reset (CPUMIPSState *env)
>      env->CP0_Random = env->tlb->nb_tlb - 1;
>      env->tlb->tlb_in_use = env->tlb->nb_tlb;
>      env->CP0_Wired = 0;
> -    /* SMP not implemented */
> -    env->CP0_EBase = 0x80000000;
> +    env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF);
>      env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
>      /* vectored interrupts not implemented, timer on int 7,
>         no performance counters. */
> -- 
> 1.7.1.GIT
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

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