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List: qemu-commits
Subject: [Qemu-commits] [qemu/qemu] 723d3a: tcg: Fix register move type in tcg_out_ld_helper_ret
From: Richard Henderson via Qemu-commits <qemu-commits () nongnu ! org>
Date: 2023-05-31 1:07:56
Message-ID: qemu/qemu/push/refs/heads/master/f89f54-51bdb0 () github ! com
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Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 723d3a276f3ea3efb4d4deb4c1150168db464dba
https://github.com/qemu/qemu/commit/723d3a276f3ea3efb4d4deb4c1150168db464dba
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Fix register move type in tcg_out_ld_helper_ret
The first move was incorrectly using TCG_TYPE_I32 while the second
move was correctly using TCG_TYPE_REG. This prevents a 64-bit host
from moving all 128-bits of the return value.
Fixes: ebebea53ef8 ("tcg: Support TCG_TYPE_I128 in tcg_out_{ld,st}_helper_{args,ret}")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9e0e6a7e8e2351ca757f08f491ef99bbc2afd548
https://github.com/qemu/qemu/commit/9e0e6a7e8e2351ca757f08f491ef99bbc2afd548
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M accel/tcg/ldst_atomicity.c.inc
Log Message:
-----------
accel/tcg: Fix check for page writeability in load_atomic16_or_exit
PAGE_WRITE is current writability, as modified by TB protection;
PAGE_WRITE_ORG is the original page writability.
Fixes: cdfac37be0d ("accel/tcg: Honor atomicity of loads")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6479dd74f14d51f207509aa1b77b039b7bd32bff
https://github.com/qemu/qemu/commit/6479dd74f14d51f207509aa1b77b039b7bd32bff
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M include/qemu/int128.h
M meson.build
Log Message:
-----------
meson: Split test for __int128_t type from __int128_t arithmetic
Older versions of clang have missing runtime functions for arithmetic
with -fsanitize=undefined (see 464e3671f9d5c), so we cannot use
__int128_t for implementing Int128. But __int128_t is present,
data movement works, and it can be used for atomic128.
Probe for both CONFIG_INT128_TYPE and CONFIG_INT128, adjust
qemu/int128.h to define Int128Alias if CONFIG_INT128_TYPE,
and adjust the meson probe for atomics to use has_int128_type.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 480dfba2c9fe4e67f0d1f01a20c9a0fd09587ece
https://github.com/qemu/qemu/commit/480dfba2c9fe4e67f0d1f01a20c9a0fd09587ece
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
A host/include/x86_64/host/atomic128-ldst.h
Log Message:
-----------
qemu/atomic128: Add x86_64 atomic128-ldst.h
With CPUINFO_ATOMIC_VMOVDQA, we can perform proper atomic
load/store without cmpxchg16b.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 098d0fc10d26e5a7d73cce93d145136c595399d6
https://github.com/qemu/qemu/commit/098d0fc10d26e5a7d73cce93d145136c595399d6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
Log Message:
-----------
tcg/i386: Support 128-bit load/store
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d67bcbddce95c44f9033f9548a6aca2c50a65f22
https://github.com/qemu/qemu/commit/d67bcbddce95c44f9033f9548a6aca2c50a65f22
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Rename temporaries
We will need to allocate a second general-purpose temporary.
Rename the existing temps to add a distinguishing number.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: da4d0d95b41b97a2a2e0907da14830151f56d851
https://github.com/qemu/qemu/commit/da4d0d95b41b97a2a2e0907da14830151f56d851
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Reserve TCG_REG_TMP1, TCG_REG_TMP2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 285a691fd2fe083c919c8ff06a8531ffc5cd7152
https://github.com/qemu/qemu/commit/285a691fd2fe083c919c8ff06a8531ffc5cd7152
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tcg/aarch64/tcg-target-con-set.h
M tcg/aarch64/tcg-target-con-str.h
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Simplify constraints on qemu_ld/st
Adjust the softmmu tlb to use TMP[0-2], not any of the normally available
registers. Since we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 929124ec0bdbfac11ae27378976e5799ca0d54cc
https://github.com/qemu/qemu/commit/929124ec0bdbfac11ae27378976e5799ca0d54cc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tcg/aarch64/tcg-target-con-set.h
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
Log Message:
-----------
tcg/aarch64: Support 128-bit load/store
With FEAT_LSE2, LDP/STP suffices. Without FEAT_LSE2, use LDXP+STXP
16-byte atomicity is required and LDP/STP otherwise.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 526cd4ec01fed36a2a6937fe54eb80d6d7f4c4e4
https://github.com/qemu/qemu/commit/526cd4ec01fed36a2a6937fe54eb80d6d7f4c4e4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tcg/ppc/tcg-target-con-set.h
M tcg/ppc/tcg-target-con-str.h
M tcg/ppc/tcg-target.c.inc
M tcg/ppc/tcg-target.h
Log Message:
-----------
tcg/ppc: Support 128-bit load/store
Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required.
Note that these instructions do not require 16-byte alignment.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4caad79f8d60a5df20ceed1c396724af745c9512
https://github.com/qemu/qemu/commit/4caad79f8d60a5df20ceed1c396724af745c9512
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Support 128-bit load/store
Use LPQ/STPQ when 16-byte atomicity is required.
Note that these instructions require 16-byte alignment.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: af844a1149691f774caeff3265af905602a98645
https://github.com/qemu/qemu/commit/af844a1149691f774caeff3265af905602a98645
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M accel/tcg/ldst_atomicity.c.inc
A host/include/generic/host/load-extract-al16-al8.h
Log Message:
-----------
accel/tcg: Extract load_atom_extract_al16_or_al8 to host header
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b3f4144fa930655b302c45d5a9284eb7b26a34bc
https://github.com/qemu/qemu/commit/b3f4144fa930655b302c45d5a9284eb7b26a34bc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M accel/tcg/ldst_atomicity.c.inc
A host/include/generic/host/store-insert-al16.h
Log Message:
-----------
accel/tcg: Extract store_atom_insert_al16 to host header
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a8bde8da47ee67e96ebee56f1f53776bd7739382
https://github.com/qemu/qemu/commit/a8bde8da47ee67e96ebee56f1f53776bd7739382
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
A host/include/x86_64/host/load-extract-al16-al8.h
Log Message:
-----------
accel/tcg: Add x86_64 load_atom_extract_al16_or_al8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 129fe7cddb25f35eb9822b39bde21febc6876d50
https://github.com/qemu/qemu/commit/129fe7cddb25f35eb9822b39bde21febc6876d50
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
A host/include/aarch64/host/load-extract-al16-al8.h
Log Message:
-----------
accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: dd906a37c7abc00b38cbe421e7f397df097ac420
https://github.com/qemu/qemu/commit/dd906a37c7abc00b38cbe421e7f397df097ac420
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
A host/include/aarch64/host/store-insert-al16.h
Log Message:
-----------
accel/tcg: Add aarch64 store_atom_insert_al16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 194339461bd3764a439af4aff6a63de764fd4c2b
https://github.com/qemu/qemu/commit/194339461bd3764a439af4aff6a63de764fd4c2b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.h
M tcg/mips/tcg-target.h
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target.h
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITS
The last use was removed by e77c89fb086a.
Fixes: e77c89fb086a ("cputlb: Remove static tlb sizing")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9b5acc563367149c27bc7a4b464f98bf06eeb59a
https://github.com/qemu/qemu/commit/9b5acc563367149c27bc7a4b464f98bf06eeb59a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M scripts/decodetree.py
Log Message:
-----------
decodetree: Add --test-for-error
Invert the exit code, for use with the testsuite.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2fd2eb5a247e641adc36a67318a791b417afea46
https://github.com/qemu/qemu/commit/2fd2eb5a247e641adc36a67318a791b417afea46
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M scripts/decodetree.py
Log Message:
-----------
decodetree: Fix recursion in prop_format and build_tree
Two copy-paste errors walking the parse tree.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f26044717679331ba31ba9bb911e059a13a49599
https://github.com/qemu/qemu/commit/f26044717679331ba31ba9bb911e059a13a49599
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M scripts/decodetree.py
Log Message:
-----------
decodetree: Diagnose empty pattern group
Test err_pattern_group_empty.decode failed with exception:
Traceback (most recent call last):
File "./scripts/decodetree.py", line 1424, in <module> main()
File "./scripts/decodetree.py", line 1342, in main toppat.build_tree()
File "./scripts/decodetree.py", line 627, in build_tree
self.tree = self.__build_tree(self.pats, self.fixedbits,
File "./scripts/decodetree.py", line 607, in __build_tree
fb = i.fixedbits & innermask
TypeError: unsupported operand type(s) for &: 'NoneType' and 'int'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 036cc75ca0bff26bfe75dc721e641d812cad3c09
https://github.com/qemu/qemu/commit/036cc75ca0bff26bfe75dc721e641d812cad3c09
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M scripts/decodetree.py
Log Message:
-----------
decodetree: Do not remove output_file from /dev
Nor report any PermissionError on remove.
The primary purpose is testing with -o /dev/null.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 656666dc7d1b8508b1a528367e683ad2af5960a3
https://github.com/qemu/qemu/commit/656666dc7d1b8508b1a528367e683ad2af5960a3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
R tests/decode/check.sh
A tests/decode/meson.build
M tests/meson.build
Log Message:
-----------
tests/decode: Convert tests to meson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7e62609353b88d9aeee9715b534588af351075af
https://github.com/qemu/qemu/commit/7e62609353b88d9aeee9715b534588af351075af
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M docs/devel/decodetree.rst
Log Message:
-----------
docs: Document decodetree named field syntax
Document the named field syntax that we want to implement for the
decodetree script. This allows a field to be defined in terms of
some other field that the instruction pattern has already set, for
example:
%sz_imm 10:3 sz:3 !function=expand_sz_imm
to allow a function to be passed both an immediate field from the
instruction and also a sz value which might have been specified by
the instruction pattern directly (sz=1, etc) rather than being a
simple field within the instruction.
Note that the restriction on not having the format referring to the
pattern and the pattern referring to the format simultaneously is a
restriction of the decoder generator rather than inherently being a
silly thing to do.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230523120447.728365-3-peter.maydell@linaro.org>
Commit: aeac22ba1e91a40d1d831cb02a1935391e67c7e2
https://github.com/qemu/qemu/commit/aeac22ba1e91a40d1d831cb02a1935391e67c7e2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M scripts/decodetree.py
Log Message:
-----------
scripts/decodetree: Pass lvalue-formatter function to str_extract()
To support referring to other named fields in field definitions, we
need to pass the str_extract() method a function which tells it how
to emit the code for a previously initialized named field. (In
Pattern::output_code() the other field will be "u.f_foo.field", and
in Format::output_extract() it is "a->field".)
Refactor the two callsites that currently do "output code to
initialize each field", and have them pass a lambda that defines how
to format the lvalue in each case. This is then used both in
emitting the LHS of the assignment and also passed down to
str_extract() as a new argument (unused at the moment, but will be
used in the following patch).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230523120447.728365-4-peter.maydell@linaro.org>
Commit: 36d612448273d0c295f519d9df3b10208177487a
https://github.com/qemu/qemu/commit/36d612448273d0c295f519d9df3b10208177487a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M scripts/decodetree.py
Log Message:
-----------
scripts/decodetree: Implement a topological sort
To support named fields, we will need to be able to do a topological
sort (so that we ensure that we output the assignment to field A
before the assignment to field B if field B refers to field A by
name). The good news is that there is a tsort in the python standard
library; the bad news is that it was only added in Python 3.9.
To bridge the gap between our current minimum supported Python
version and 3.9, provide a local implementation that has the
same API as the stdlib version for the parts we care about.
In future when QEMU's minimum Python version requirement reaches
3.9 we can delete this code and replace it with an 'import' line.
The core of this implementation is based on
https://code.activestate.com/recipes/578272-topological-sort/
which is MIT-licensed.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230523120447.728365-5-peter.maydell@linaro.org>
Commit: 7e6c28be2739c2286fe09702adef4740d9a1ed41
https://github.com/qemu/qemu/commit/7e6c28be2739c2286fe09702adef4740d9a1ed41
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M scripts/decodetree.py
Log Message:
-----------
scripts/decodetree: Implement named field support
Implement support for named fields, i.e. where one field is defined
in terms of another, rather than directly in terms of bits extracted
from the instruction.
The new method referenced_fields() on all the Field classes returns a
list of fields that this field references. This just passes through,
except for the new NamedField class.
We can then use referenced_fields() to:
* construct a list of 'dangling references' for a format or
pattern, which is the fields that the format/pattern uses but
doesn't define itself
* do a topological sort, so that we output "field = value"
assignments in an order that means that we assign a field before
we reference it in a subsequent assignment
* check when we output the code for a pattern whether we need to
fill in the format fields before or after the pattern fields, and
do other error checking
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230523120447.728365-6-peter.maydell@linaro.org>
Commit: 276d77de503e8f5f5cbd3f7d94302ca12d1d982e
https://github.com/qemu/qemu/commit/276d77de503e8f5f5cbd3f7d94302ca12d1d982e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
A tests/decode/err_field10.decode
A tests/decode/err_field7.decode
A tests/decode/err_field8.decode
A tests/decode/err_field9.decode
M tests/decode/meson.build
A tests/decode/succ_named_field.decode
Log Message:
-----------
tests/decode: Add tests for various named-field cases
Add some tests for various cases of named-field use, both ones that
should work and ones that should be diagnosed as errors.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230523120447.728365-7-peter.maydell@linaro.org>
Commit: 7f027ee0ce1f79302acd7330d796fb7a9e2529b1
https://github.com/qemu/qemu/commit/7f027ee0ce1f79302acd7330d796fb7a9e2529b1
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tests/avocado/virtio-gpu.py
Log Message:
-----------
tests/avocado/virtio-gpu: Cancel test if drm rendering is not available
The test_vhost_user_vga_virgl test currently fails on some CI
machines with:
qemu-system-x86_64: egl: no drm render node available
qemu-system-x86_64: egl: render node init failed
The other test in this file already checks whether there is
an error while starting QEMU - we should do the same for the
test_vhost_user_vga_virgl test, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230530180330.48722-1-thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 51bdb0b57a2d9e84d6915fbae7b5d76c8820cf3c
https://github.com/qemu/qemu/commit/51bdb0b57a2d9e84d6915fbae7b5d76c8820cf3c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M accel/tcg/ldst_atomicity.c.inc
M docs/devel/decodetree.rst
A host/include/aarch64/host/load-extract-al16-al8.h
A host/include/aarch64/host/store-insert-al16.h
A host/include/generic/host/load-extract-al16-al8.h
A host/include/generic/host/store-insert-al16.h
A host/include/x86_64/host/atomic128-ldst.h
A host/include/x86_64/host/load-extract-al16-al8.h
M include/qemu/int128.h
M meson.build
M scripts/decodetree.py
M tcg/aarch64/tcg-target-con-set.h
M tcg/aarch64/tcg-target-con-str.h
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
M tcg/mips/tcg-target.h
M tcg/ppc/tcg-target-con-set.h
M tcg/ppc/tcg-target-con-str.h
M tcg/ppc/tcg-target.c.inc
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target.h
M tcg/tcg.c
M tcg/tci/tcg-target.h
R tests/decode/check.sh
A tests/decode/err_field10.decode
A tests/decode/err_field7.decode
A tests/decode/err_field8.decode
A tests/decode/err_field9.decode
A tests/decode/meson.build
A tests/decode/succ_named_field.decode
M tests/meson.build
Log Message:
-----------
Merge tag 'pull-tcg-20230530' of https://gitlab.com/rth7680/qemu into staging
Improvements to 128-bit atomics:
- Separate __int128_t type and arithmetic detection
- Support 128-bit load/store in backend for i386, aarch64, ppc64, s390x
- Accelerate atomics via host/include/
Decodetree:
- Add named field syntax
- Move tests to meson
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# gpg: Signature made Tue 30 May 2023 11:58:37 AM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20230530' of https://gitlab.com/rth7680/qemu: (27 commits)
tests/decode: Add tests for various named-field cases
scripts/decodetree: Implement named field support
scripts/decodetree: Implement a topological sort
scripts/decodetree: Pass lvalue-formatter function to str_extract()
docs: Document decodetree named field syntax
tests/decode: Convert tests to meson
decodetree: Do not remove output_file from /dev
decodetree: Diagnose empty pattern group
decodetree: Fix recursion in prop_format and build_tree
decodetree: Add --test-for-error
tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITS
accel/tcg: Add aarch64 store_atom_insert_al16
accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8
accel/tcg: Add x86_64 load_atom_extract_al16_or_al8
accel/tcg: Extract store_atom_insert_al16 to host header
accel/tcg: Extract load_atom_extract_al16_or_al8 to host header
tcg/s390x: Support 128-bit load/store
tcg/ppc: Support 128-bit load/store
tcg/aarch64: Support 128-bit load/store
tcg/aarch64: Simplify constraints on qemu_ld/st
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/f89f54d52bf8...51bdb0b57a2d
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