[prev in list] [next in list] [prev in thread] [next in thread] 

List:       qemu-arm
Subject:    Re: [PATCH] target/arm: Fix SVE STR increment
From:       Richard Henderson <richard.henderson () linaro ! org>
Date:       2023-10-31 14:08:27
Message-ID: c0479a28-1e95-480a-abaf-faf8ee12743e () linaro ! org
[Download RAW message or body]

On 10/31/23 03:52, Peter Maydell wrote:
> On Mon, 30 Oct 2023 at 19:04, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> The previous change missed updating one of the increments.
>>
>> Cc: qemu-stable@nongnu.org
>> Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   target/arm/tcg/translate-sve.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
>> index 7b39962f20..fc4220114d 100644
>> --- a/target/arm/tcg/translate-sve.c
>> +++ b/target/arm/tcg/translate-sve.c
>> @@ -4294,7 +4294,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
>>           t0 = tcg_temp_new_i64();
>>           t1 = tcg_temp_new_i64();
>>           t16 = tcg_temp_new_i128();
>> -        for (i = 0; i < len_align; i += 8) {
>> +        for (i = 0; i < len_align; i += 16) {
>>               tcg_gen_ld_i64(t0, base, vofs + i);
>>               tcg_gen_ld_i64(t1, base, vofs + i + 8);
>>               tcg_gen_concat_i64_i128(t16, t0, t1);
>> --
> 
> This fixes the test case I have for vector lengths of 64 bytes
> and below, but vector lengths above that (eg 128 bytes) still
> misbehave in a different way (only every other set of 8 bytes
> gets stored). Presumably that's a different bug somewhere else?

Oh yes -- enable-debug yields

qemu-aarch64: ../src/tcg/tcg-op-ldst.c:712: tcg_gen_qemu_st_i128_chk: Assertion `(memop & 
MO_SIZE) == MO_128' failed.


r~


[prev in list] [next in list] [prev in thread] [next in thread]