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List: qemu-arm
Subject: [PATCH 06/15] hw/timer/arm_timer: CamelCase rename arm_timer_state -> ArmTimerState
From: Philippe Mathieu-Daudé <philmd () linaro ! org>
Date: 2023-05-31 20:35:50
Message-ID: 20230531203559.29140-7-philmd () linaro ! org
[Download RAW message or body]
Following docs/devel/style.rst guidelines, rename arm_timer_state
as ArmTimerState.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/timer/arm_timer.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c
index fc8d25b0dc..2cd8c99b4e 100644
--- a/hw/timer/arm_timer.c
+++ b/hw/timer/arm_timer.c
@@ -36,11 +36,11 @@ typedef struct {
int freq;
int int_level;
qemu_irq irq;
-} arm_timer_state;
+} ArmTimerState;
/* Check all active timers, and schedule the next timer interrupt. */
-static void arm_timer_update(arm_timer_state *s)
+static void arm_timer_update(ArmTimerState *s)
{
/* Update interrupts. */
if (s->int_level && (s->control & TIMER_CTRL_IE)) {
@@ -52,7 +52,7 @@ static void arm_timer_update(arm_timer_state *s)
static uint32_t arm_timer_read(void *opaque, hwaddr offset)
{
- arm_timer_state *s = opaque;
+ ArmTimerState *s = opaque;
switch (offset >> 2) {
case 0: /* TimerLoad */
@@ -79,7 +79,7 @@ static uint32_t arm_timer_read(void *opaque, hwaddr offset)
* Reset the timer limit after settings have changed.
* May only be called from inside a ptimer transaction block.
*/
-static void arm_timer_recalibrate(arm_timer_state *s, int reload)
+static void arm_timer_recalibrate(ArmTimerState *s, int reload)
{
uint32_t limit;
@@ -99,7 +99,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload)
static void arm_timer_write(void *opaque, hwaddr offset,
uint32_t value)
{
- arm_timer_state *s = opaque;
+ ArmTimerState *s = opaque;
int freq;
switch (offset >> 2) {
@@ -154,7 +154,7 @@ static void arm_timer_write(void *opaque, hwaddr offset,
static void arm_timer_tick(void *opaque)
{
- arm_timer_state *s = opaque;
+ ArmTimerState *s = opaque;
s->int_level = 1;
arm_timer_update(s);
}
@@ -164,19 +164,19 @@ static const VMStateDescription vmstate_arm_timer = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
- VMSTATE_UINT32(control, arm_timer_state),
- VMSTATE_UINT32(limit, arm_timer_state),
- VMSTATE_INT32(int_level, arm_timer_state),
- VMSTATE_PTIMER(timer, arm_timer_state),
+ VMSTATE_UINT32(control, ArmTimerState),
+ VMSTATE_UINT32(limit, ArmTimerState),
+ VMSTATE_INT32(int_level, ArmTimerState),
+ VMSTATE_PTIMER(timer, ArmTimerState),
VMSTATE_END_OF_LIST()
}
};
-static arm_timer_state *arm_timer_init(uint32_t freq)
+static ArmTimerState *arm_timer_init(uint32_t freq)
{
- arm_timer_state *s;
+ ArmTimerState *s;
- s = g_new0(arm_timer_state, 1);
+ s = g_new0(ArmTimerState, 1);
s->freq = freq;
s->control = TIMER_CTRL_IE;
@@ -198,7 +198,7 @@ struct SP804State {
SysBusDevice parent_obj;
MemoryRegion iomem;
- arm_timer_state *timer[2];
+ ArmTimerState *timer[2];
uint32_t freq0, freq1;
int level[2];
qemu_irq irq;
@@ -343,7 +343,7 @@ struct IntegratorPitState {
SysBusDevice parent_obj;
MemoryRegion iomem;
- arm_timer_state *timer[3];
+ ArmTimerState *timer[3];
};
static uint64_t icp_pit_read(void *opaque, hwaddr offset,
--
2.38.1
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