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List:       oprofile-list
Subject:    Updates to the oprofile-tests
From:       William Cohen <wcohen () redhat ! com>
Date:       2009-12-23 14:42:24
Message-ID: 4B322C50.4010907 () redhat ! com
[Download RAW message or body]

It has been a while since the oprofile testsuite has been updated. I went 
through it Tuesday and added support for a number of architectures. In 
particular added tests for the newer i386 and power variants. If it looks okay, 
I will check it in.

-Will

["tests-update.patch" (text/plain)]

? testsuite/dbg.log
Index: testsuite/lib/op_events.exp
===================================================================
RCS file: /cvsroot/oprofile/oprofile-tests/testsuite/lib/op_events.exp,v
retrieving revision 1.2
diff -u -r1.2 op_events.exp
--- testsuite/lib/op_events.exp	28 Jun 2007 18:24:26 -0000	1.2
+++ testsuite/lib/op_events.exp	23 Dec 2009 05:45:24 -0000
@@ -157,6 +157,22 @@
 	}                                           \
     }
 
+set op_event_table(arch_perf)                       \
+    {                                               \
+	{                                           \
+             {0 INST_RETIRED      0 500000}         \
+             {1 CPU_CLK_UNHALTED  0 500000}         \
+	}                                           \
+	{                                           \
+             {0 LLC_MISSES        0x41 500000}      \
+             {1 LLC_REFS          0x4f 500000}      \
+	}                                           \
+	{                                           \
+             {0 BR_INST_RETIRED   0 500000}         \
+             {1 BR_MISS_PRED_RETIRED 0 500000}      \
+	}                                           \
+    }
+
 set op_event_table(athlon)                          \
     {                                               \
 	{                                           \
@@ -198,7 +214,7 @@
     {                                               \
     }
 
-set op_event_table(xscale1)                         \
+set op_event_table(gen_arm)                         \
     {                                               \
 	{                                           \
              {1 INSN_EXECUTED     0 500000}         \
@@ -206,19 +222,19 @@
 	}                                           \
 	{                                           \
              {1 DCACHE_MISS       0 500000}         \
-             {2 DCACHE_ACCES      0 500000}         \
+             {2 DCACHE_ACCESS     0 500000}         \
 	}                                           \
     }
 
-set op_event_table(xscale2)                         \
+set op_event_table(arm7)                            \
     {                                               \
 	{                                           \
              {1 INSN_EXECUTED     0 500000}         \
              {0 CPU_CYCLES        0 500000}         \
 	}                                           \
 	{                                           \
-             {1 DCACHE_MISS       0 500000}         \
-             {2 DCACHE_ACCES      0 500000}         \
+             {1 DCACHE_REFILL      0 500000}        \
+             {2 DCACHE_ACCESS      0 500000}        \
 	}                                           \
     }
 
@@ -274,6 +290,19 @@
 	}                                           \
     }
 
+set op_event_table(power5pp)                        \
+    {                                               \
+	{                                           \
+	    {1 CYCLES 0 500000}                     \
+	}                                           \
+	{                                           \
+	    {0 PM_BR_UNCOND_GRP43 0 500000}         \
+	    {1 PM_BR_PRED_TA_GRP43 0 500000}	    \
+	    {2 PM_BR_PRED_CR_GRP43 0 500000}	    \
+	    {3 PM_BR_PRED_CR_TA_GRP43 0 500000}	    \
+	}                                           \
+    }
+
 set op_event_table(ppc970)                          \
     {						    \
         {					    \
@@ -296,6 +325,94 @@
 	}					    \
     }
 
+set op_event_table(power6)                          \
+    {                                               \
+	{                                           \
+	    {3 CYCLES 0 500000}                     \
+	}                                           \
+	{					    \
+	    {0 PM_RUN_CYC_GRP1 0 500000}	    \
+	    {1 PM_CYC_GRP1 0 500000}		    \
+	    {3 PM_INST_CMPL_GRP1 0 500000}	    \
+	}					    \
+	{                                           \
+	    {0 PM_BR_PRED_CR_GRP3 0 500000}         \
+	    {1 PM_BR_MPRED_CR_GRP3 0 500000}        \
+	    {2 PM_BR_PRED_GRP3  0 500000}           \
+	    {3 PM_BR_MPRED_COUNT_GRP3 0 500000}     \
+        }					    \
+    }
+
+set op_event_table(power7)                          \
+    {                                               \
+	{                                           \
+	    {0 CYCLES 0 500000}                     \
+	}                                           \
+	{                                           \
+	    {0 PM_BR_PRED_GRP3 0 500000}            \
+	    {1 PM_BR_PRED_CR_GRP3 0 500000}         \
+            {2 PM_BR_PRED_CCACHE_GRP3 0 500000}     \
+	    {3 PM_BR_PRED_LSTACK_GRP3 0 500000}     \
+	    {4 PM_RUN_INST_CMPL_GRP3 0 500000}      \
+	    {5 PM_RUN_CYC_GRP3  0 500000}           \
+	}                                           \
+    }
+
+set op_event_table(ibm_compat_v1)                   \
+    {                                               \
+	{                                           \
+	    {2 CYCLES 0 500000}                     \
+	}                                           \
+	{                                           \
+	    {0 PM_DATA_FROM_L1-5_GRP3 0 500000}     \
+	    {1 PM_DATA_FROM_L2MISS_GRP3 0 500000}   \
+	    {2 PM_DATA_FROM_L3MISS_GRP3 0 500000}   \
+	    {3 PM_RUN_INST_CMPL_GRP3 0 500000}      \
+	}                                           \
+	{                                           \
+	    {0 PM_DATA_FROM_L1-5_GRP3 0 500000}     \
+	    {1 PM_DATA_FROM_L2MISS_GRP3 0 500000}   \
+	    {2 PM_DATA_FROM_L3MISS_GRP3 0 500000}   \
+	    {3 PM_RUN_INST_CMPL_GRP3 0 500000}      \
+	}                                           \
+    }
+
+set op_event_table(cell_be)                         \
+    {                                               \
+	{                                           \
+	    {0 CYCLES 0 500000}                     \
+	}                                           \
+	{                                           \
+	    {0 CYCLES 0 500000}                     \
+	    {1 SPU_CYCLES 0 500000}                 \
+	}                                           \
+	{                                           \
+	    {0 Branch_Commit 0 500000}              \
+	    {1 Branch_Flush 0 500000}               \
+	    {2 IL1_Miss_Cycles 0 500000}            \
+	    {3 PPC_Commit 0 500000}                 \
+	}                                           \
+    }
+
+#Placeholder for pa6t based
+set op_event_table(pa6t)                            \
+    {                                               \
+	{                                           \
+	    {0 CYCLES 0 500000}                     \
+	}                                           \
+	    {0 CYCLES 0 500000}                     \
+	    {3 ISS_CYCLES 0 500000}                 \
+	    {4 RET_UOP 0 500000}                    \
+	{                                           \
+	    {0 GRP3_CYCLES 0 500000}                \
+	    {1 GRP3_INST_RETIRED 0 500000}          \
+	    {2 GRP3_NXT_LINE_MISPRED__NS 0 500000}  \
+	    {3 GRP3_DIRN_MISPRED__NS 0 500000}      \
+	    {4 GRP3_TGT_ADDR_MISPRED__NS 0 500000}  \
+	    {5 GRP3_BRA_TAKEN__NS 0 500000}         \
+	}                                           \
+    }
+
 #Placeholder for rtc (shouldn't be used in tests)
 set op_event_table(rtc)                             \
     {                                               \
@@ -311,7 +428,7 @@
     }
 
 #Placeholder for mips based
-set op_event_table(mikps)                           \
+set op_event_table(mips)                           \
     {                                               \
 	{                                           \
 	}                                           \
@@ -324,10 +441,17 @@
 	}                                           \
     }
 
-#Placeholder for ppc e500 based
+#Placeholder for ppc 7450 based
 set op_event_table(ppc7450)                         \
     {                                               \
 	{                                           \
 	}                                           \
     }
  
+#Placeholder for avr32 based
+set op_event_table(avr32)                           \
+    {                                               \
+	{                                           \
+	}                                           \
+    }
+
Index: testsuite/lib/op_util.exp
===================================================================
RCS file: /cvsroot/oprofile/oprofile-tests/testsuite/lib/op_util.exp,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 op_util.exp
--- testsuite/lib/op_util.exp	23 Oct 2006 19:24:48 -0000	1.1.1.1
+++ testsuite/lib/op_util.exp	23 Dec 2009 05:45:24 -0000
@@ -91,10 +91,10 @@
 	alpha/ev67 {set type alpha}
 	17 {set type ppro}
  	i386/p6_mobile {set type ppro}
-	18 {set type xscale}
-	arm/xscale1 {set type xscale1}
-	19 {set type xscale}
-	arm/xscale2 {set type xscale2}
+	18 {set type gen_arm}
+	arm/xscale1 {set type gen_arm}
+	19 {set type gen_arm}
+	arm/xscale2 {set type gen_arm}
 	20 {set type power4}
 	ppc64/power4 {set type power4}
 	21 {set type power5}
@@ -137,6 +137,42 @@
 	ppc/7450 {set type ppc7450}
 	40 {set type core2}
  	i386/core_2 {set type core2}
+	41 {set type power6}
+	ppc64/power6 {set type power6}
+	42 {set type power970}
+	ppc64/970MP {set type power970}
+	43 {set type cell_be}
+	ppc64/cell-be {set type cell_be}
+	44 {set type athlon}
+	x86-64/family10 {set type athlon}
+	45 {set type pa6t}
+	ppc64/pa6t {set type pa6t}
+	46 {set type gen_arm}
+	arm/mpcore {set type gen_arm}
+	47 {set type gen_arm}
+	arm/armv6 {set type gen_arm}
+	48 {set type power5pp}
+	ppc64/power5++ {set type power5pp}
+	49 {set type e500}
+	ppc/e300 {set type e500}
+	50 {set type avr32}
+	avr32 {set type avr32}
+	51 {set type arm7}
+	arm/armv7 {set type arm7}
+	52 {set type arch_perf}
+ 	i386/arch_perfmon {set type arch_perf}
+	53  {set type athlon}
+	x86-64/family11h {set type athlon}
+	54 {set type power7}
+	ppc64/power7 {set type power7}
+	55 {set type ibm_compat_v1}
+	ppc64/ibm-compat-v1 {set type ibm_compat_v1}
+	56 {set type arch_perf}
+   	i386/core_i7 {set type arch_perf}
+	57 {set type arch_perf}
+	i386/atom {set type arch_perf}
+	58 {set type mips}
+	mips/loongson2 {set type mips}
     }
 
     verbose "cpu type is $type"


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