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List: oprofile-list
Subject: Support for ARM cores moving forward
From: David Rusling <david.rusling () arm ! com>
Date: 2009-09-17 14:03:50
Message-ID: C6D80056.4BAD%david.rusling () arm ! com
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Hi,
back in March, Jon Callan from ARM attempted to post a bunch of changes
to oprofile. These included support for the ARM A8 and A9 processors plus
multicore for ARM11MP and A9. These were rejected and our response
fizzled somewhat; I¹m trying to pick up the pieces and see how we can move
this forward. I¹d welcome a bit of discussion.
The fixes were:
[1] A8 support. This has been superceded by the armv7 event support in
the CVS repository. Our patches are redundant. I¹d also note that the
appropriate kernel patches matching this support is firmly in the kernel.
[2] Extending the armv7 events for the A9 and including events counted in
the SCU (snoop control unit) and L2x0 (memory controller). Rather than
invent another CPU type, one with more events, it would be good to find a
way to add in extra events by platform.
[3] Multicore. The way that this was done was to modify the events
returned from the kernel to reflect which CPU generated the event (or
whether it came from another entity in the system). Unfortunately this
raises the number of events that can be counted (see item [4] below).
Does this make sense do oprofile users want to see per-CPU counters or a
combined counter across all CPUs? For example, does a user want to see the
total icache misses or each CPU¹s icache misses? What do other multicore
architectures do?
[4] We bumped the number of events supported in op_alloc_counter.c. Mostly
because of [3] above as we were trying to report all CPUs separately.
Dave
----------------------------------------------------------------
David A Rusling, ARM Fellow
Processor Division Tools
ARM Limited
110 Fulbourn Road, Cambridge, CB1 9NJ
Tel: +44 1223 400424
----------------------------------------------------------------
--
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and \
may also be privileged. If you are not the intended recipient, please notify the \
sender immediately and do not disclose the contents to any other person, use it for \
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[Attachment #5 (text/html)]
<HTML>
<HEAD>
<TITLE>Support for ARM cores moving forward</TITLE>
</HEAD>
<BODY>
<FONT SIZE="4"><FONT FACE="Calibri, Verdana, Helvetica, Arial"><SPAN \
STYLE='font-size:11pt'>Hi,<BR> back in March, Jon Callan from \
ARM attempted to post a bunch of changes to oprofile. These included \
support for the ARM A8 and A9 processors plus multicore for ARM11MP and A9. \
These were rejected and our response fizzled somewhat; \
I’m trying to pick up the pieces and see how we can move this forward. \
I’d welcome a bit of discussion.<BR> <BR>
The fixes were:<BR>
[1] A8 support. This has been superceded by the armv7 event support \
in the CVS repository. Our patches are redundant. \
I’d also note that the appropriate kernel patches matching this \
support is firmly in the kernel.<BR> [2] Extending the armv7 events for the A9 and \
including events counted in the SCU (snoop control unit) and L2x0 (memory \
controller). Rather than invent another CPU type, one with more events, \
it would be good to find a way to add in extra events by platform.<BR> [3] Multicore. \
The way that this was done was to modify the events returned from the \
kernel to reflect which CPU generated the event (or whether it came from another \
entity in the system). Unfortunately this raises the number of events \
that can be counted (see item [4] below). Does this make sense \
– do oprofile users want to see per-CPU counters or a combined counter across \
all CPUs? For example, does a user want to see the total icache misses or \
each CPU’s icache misses? What do other multicore architectures \
do?<BR> [4] We bumped the number of events supported in op_alloc_counter.c. \
Mostly because of [3] above as we were trying to report all CPUs \
separately.<BR> <BR>
Dave<BR>
</SPAN></FONT><FONT FACE="Consolas, Courier New, Courier"><SPAN \
STYLE='font-size:10pt'>----------------------------------------------------------------<BR>
David A Rusling, ARM Fellow<BR>
Processor Division Tools<BR>
ARM Limited<BR>
110 Fulbourn Road, Cambridge, CB1 9NJ<BR>
Tel: +44 1223 400424<BR>
----------------------------------------------------------------</SPAN></FONT><FONT \
FACE="Calibri, Verdana, Helvetica, Arial"><SPAN STYLE='font-size:11pt'> <BR> \
</SPAN></FONT></FONT> <DIV> </DIV>-- <br>IMPORTANT NOTICE: The contents of this \
email and any attachments are confidential and may also be privileged. If you are not \
the intended recipient, please notify the sender immediately and do not disclose the \
contents to any other person, use it for any purpose, or store or copy the \
information in any medium. Thank you.</BODY> </HTML>
------------------------------------------------------------------------------
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