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List:       oprofile-commits
Subject:    [oprof-cvs] CVS: oprofile/libop op_cpu_type.c, 1.52,
From:       "Suravee Suthikulpanit" <ssuthiku () users ! sourceforge ! net>
Date:       2009-05-07 14:20:18
Message-ID: E1M24SQ-0004Mw-LI () 23jxhf1 ! ch3 ! sourceforge ! com
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Update of /cvsroot/oprofile/oprofile/libop
In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv16271/libop

Modified Files:
	op_cpu_type.c op_cpu_type.h op_events.c op_hw_specific.h 
Log Message:
Add atom, core_i7, nehalem support


Index: op_cpu_type.c
===================================================================
RCS file: /cvsroot/oprofile/oprofile/libop/op_cpu_type.c,v
retrieving revision 1.52
retrieving revision 1.53
diff -u -p -d -r1.52 -r1.53
--- op_cpu_type.c	7 May 2009 13:07:38 -0000	1.52
+++ op_cpu_type.c	7 May 2009 14:20:16 -0000	1.53
@@ -80,6 +80,8 @@ static struct cpu_descr const cpu_descrs
 	{ "AMD64 family11h", "x86-64/family11h", CPU_FAMILY11H, 4 },
 	{ "ppc64 POWER7", "ppc64/power7", CPU_PPC64_POWER7, 6 },
 	{ "ppc64 compat version 1", "ppc64/ibm-compat-v1", CPU_PPC64_IBM_COMPAT_V1, 4 },
+   	{ "Intel Core/i7", "i386/core_i7", CPU_CORE_I7, 4 },
+   	{ "Intel Atom", "i386/atom", CPU_ATOM, 2 },
 };
  
 static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);

Index: op_cpu_type.h
===================================================================
RCS file: /cvsroot/oprofile/oprofile/libop/op_cpu_type.h,v
retrieving revision 1.45
retrieving revision 1.46
diff -u -p -d -r1.45 -r1.46
--- op_cpu_type.h	7 May 2009 13:07:38 -0000	1.45
+++ op_cpu_type.h	7 May 2009 14:20:16 -0000	1.46
@@ -77,6 +77,8 @@ typedef enum {
 	CPU_FAMILY11H, /**< AMD family 11h */
 	CPU_PPC64_POWER7, /**< ppc64 POWER7 family */
 	CPU_PPC64_IBM_COMPAT_V1, /**< IBM PPC64 processor compat mode version 1 */
+   	CPU_CORE_I7, /* Intel Core i7, Nehalem */
+   	CPU_ATOM, /* First generation Intel Atom */
 	MAX_CPU_TYPE
 } op_cpu;
 

Index: op_events.c
===================================================================
RCS file: /cvsroot/oprofile/oprofile/libop/op_events.c,v
retrieving revision 1.95
retrieving revision 1.96
diff -u -p -d -r1.95 -r1.96
--- op_events.c	7 May 2009 13:07:38 -0000	1.95
+++ op_events.c	7 May 2009 14:20:16 -0000	1.96
@@ -944,6 +944,8 @@ void op_default_event(op_cpu cpu_type, s
 		case CPU_FAMILY10:
 		case CPU_ARCH_PERFMON:
 		case CPU_FAMILY11H:
+ 		case CPU_ATOM:
+ 		case CPU_CORE_I7:
 			descr->name = "CPU_CLK_UNHALTED";
 			break;
 

Index: op_hw_specific.h
===================================================================
RCS file: /cvsroot/oprofile/oprofile/libop/op_hw_specific.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -p -d -r1.1 -r1.2
--- op_hw_specific.h	28 Aug 2008 21:57:46 -0000	1.1
+++ op_hw_specific.h	7 May 2009 14:20:16 -0000	1.2
@@ -11,11 +11,54 @@
 
 #define num_to_mask(x) ((1U << (x)) - 1)
 
+static inline int cpuid_vendor(char *vnd)
+{
+	union {
+		struct {
+			unsigned b,d,c;
+		};
+		char v[12];
+	} v;
+	unsigned eax;
+	asm("cpuid" : "=a" (eax), "=b" (v.b), "=c" (v.c), "=d" (v.d) : "0" (0));
+	return !strncmp(v.v, vnd, 12);
+}
+
+/* Work around Nehalem spec update AAJ79: CPUID incorrectly indicates
+   unhalted reference cycle architectural event is supported. We assume
+   steppings after C0 report correct data in CPUID. */
+static inline void workaround_nehalem_aaj79(unsigned *ebx)
+{
+	union {
+		unsigned eax;
+		struct {
+			unsigned stepping : 4;
+			unsigned model : 4;
+			unsigned family : 4;
+			unsigned type : 2;
+			unsigned res : 2;
+			unsigned ext_model : 4;
+			unsigned ext_family : 8;
+			unsigned res2 : 4;
+		};
+	} v;
+	unsigned model;
+
+	if (!cpuid_vendor("GenuineIntel"))
+		return;
+	asm("cpuid" : "=a" (v.eax) : "0" (1) : "ecx","ebx","edx");
+	model = (v.ext_model << 4) + v.model;
+	if (v.family != 6 || model != 26 || v.stepping > 4)
+		return;
+	*ebx |= (1 << 2);	/* disable unsupported event */
+}
+
 static inline unsigned arch_get_filter(op_cpu cpu_type)
 {
 	if (cpu_type == CPU_ARCH_PERFMON) { 
 		unsigned ebx, eax;
 		asm("cpuid" : "=a" (eax), "=b" (ebx) : "0" (0xa) : "ecx","edx");
+		workaround_nehalem_aaj79(&ebx);
 		return ebx & num_to_mask(eax >> 24);
 	}
 	return 0;


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