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List:       openocd-development
Subject:    [PATCH]: 31b72c26a9 flash/nor/stm32f1x: use is_riscv() helper instead of target type name
From:       gerrit () openocd ! org
Date:       2022-05-26 11:54:14
Message-ID: 20220526115414.616E516D () openocd ! org
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This is an automated email from Gerrit.

"Tomas Vanek <vanekt@fbl.cz>" just uploaded a new patch set to Gerrit, which you can \
find at https://review.openocd.org/c/openocd/+/7000

-- gerrit

commit 31b72c26a9abc3c67a94d1962478db1366a73479
Author: Tomas Vanek <vanekt@fbl.cz>
Date:   Thu May 26 11:40:15 2022 +0200

    flash/nor/stm32f1x: use is_riscv() helper instead of target type name
    
    Change-Id: Idba211d8df5c2d429b3bb825fd2a0e31273bb759
    Signed-off-by: Tomas Vanek <vanekt@fbl.cz>

diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index c750ff0803..ecafc6e3b9 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -32,6 +32,7 @@
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
 #include <target/cortex_m.h>
+#include <target/riscv/riscv.h>		/* for GD32VF103 */
 
 /* stm32x register locations */
 
@@ -773,14 +774,13 @@ static int stm32x_get_property_addr(struct target *target, \
struct stm32x_propert  return ERROR_OK;
 	case CORTEX_M_PARTNO_INVALID:
 		/* Check for GD32VF103 with RISC-V CPU */
-		if (strcmp(target_type_name(target), "riscv") == 0
-				&& target_address_bits(target) == 32) {
-			/* There is nothing like arm common_magic in riscv_info_t
-			 * check text name of target and if target is 32-bit
-			 */
-			addr->device_id = 0xE0042000;
-			addr->flash_size = 0x1FFFF7E0;
-			return ERROR_OK;
+		if (target->arch_info) {
+			struct riscv_info *riscv = riscv_info(target);
+			if (is_riscv(riscv) && target_address_bits(target) == 32) {
+				addr->device_id = 0xE0042000;
+				addr->flash_size = 0x1FFFF7E0;
+				return ERROR_OK;
+			}
 		}
 		/* fallthrough */
 	default:

-- 


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