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List:       openocd-development
Subject:    [PATCH]: e12955c1b aarch64: add mask ISR register immediate
From:       gerrit () openocd ! org
Date:       2021-08-24 14:24:42
Message-ID: 20210824142442.55FD1291 () openocd ! org
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This is an automated email from Gerrit.

"Dietmar May <dietmar.may@outlook.com>" just uploaded a new patch set to Gerrit, \
which you can find at https://review.openocd.org/c/openocd/+/6475

-- gerrit

commit e12955c1b1c8670c2793323d31f8ed7b77dba0b8
Author: Dietmar May <dietmar.may@outlook.com>
Date:   Thu Aug 19 11:13:10 2021 -0400

    aarch64: add mask ISR register immediate
    
    When debugging a boot loader, it's important to prevent spurious
    interrupts from happening before the interrupt vector table can be
    intialized by bootloader code. OpenOCD currently controls these during
    breakpoint handling.
    
    This patch adds two options - mask, unmask - to support immediately
    switching off (or on) interrupts via the ISR register.
    
    proc reset_init { } {
        set _t [target current]
         $_t aarch64 maskisr mask
    }
    
    Signed-off-by: Dietmar May <dietmar.may@outlook.com>
    Change-Id: I0569b5f1b9c82b7c6de480cc36527bb7d92da0e8

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index f71c735a8..9e8a7cd91 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2930,27 +2930,45 @@ COMMAND_HANDLER(aarch64_mask_interrupts_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct aarch64_common *aarch64 = target_to_aarch64(target);
 
+	enum aarch64_isr_immed {
+		AARCH64_ISR_IMMED_ON = -3,
+		AARCH64_ISR_IMMED_OFF = -2,
+	};
+
 	static const struct jim_nvp nvp_maskisr_modes[] = {
 		{ .name = "off", .value = AARCH64_ISRMASK_OFF },
 		{ .name = "on", .value = AARCH64_ISRMASK_ON },
+		{ .name = "mask", .value = AARCH64_ISR_IMMED_OFF },
+		{ .name = "unmask", .value = AARCH64_ISR_IMMED_ON },
 		{ .name = NULL, .value = -1 },
 	};
 	const struct jim_nvp *n;
 
+	int retval = ERROR_OK;
+
 	if (CMD_ARGC > 0) {
 		n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
 		if (!n->name) {
-			LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]);
+			LOG_ERROR("Unknown parameter: %s - should be off or on; immediate - use mask or \
unmask)", CMD_ARGV[0]);  return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 
-		aarch64->isrmasking_mode = n->value;
+		if(n->value == AARCH64_ISR_IMMED_OFF) {
+			/* mask (disable) interrupts immediately - todo save current ISR mask */
+			retval = aarch64_set_dscr_bits(target, 0x3 << 22, 0x3 << 22);
+		} else if(n->value == AARCH64_ISR_IMMED_ON) {
+			/* unmask all interrupts immediately - todo restore saved ISR mask */
+			retval = aarch64_set_dscr_bits(target, 0x3 << 22, 0);
+		} else {
+			aarch64->isrmasking_mode = n->value;
+		}
+	} else {
+		n = jim_nvp_value2name_simple(nvp_maskisr_modes, aarch64->isrmasking_mode);
 	}
 
-	n = jim_nvp_value2name_simple(nvp_maskisr_modes, aarch64->isrmasking_mode);
-	command_print(CMD, "aarch64 interrupt mask %s", n->name);
+	command_print(CMD, "aarch64 interrupt %s", n->name);
 
-	return ERROR_OK;
+	return retval;
 }
 
 /* Move to ARM register from coprocessor
@@ -3247,7 +3265,7 @@ static const struct command_registration \
                aarch64_exec_command_handlers[] = {
 		.handler = aarch64_mask_interrupts_command,
 		.mode = COMMAND_ANY,
 		.help = "mask aarch64 interrupts during single-step",
-		.usage = "['on'|'off']",
+		.usage = "['on'|'off']|['mask'|'unmask']",
 	},
 	{
 		.name = "mcr",

-- 


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