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List:       openocd-development
Subject:    [OpenOCD-devel] [PATCH]: 2177468 coding style: fix space separation
From:       gerrit () openocd ! org (gerrit)
Date:       2020-04-27 15:59:24
Message-ID: 20200427155924.758AB4A0AE8 () mail ! openocd ! org
[Download RAW message or body]

This is an automated email from Gerrit.

Antonio Borneo (borneo.antonio@gmail.com) just uploaded a new patch set to Gerrit, \
which you can find at http://openocd.zylin.com/5627

-- gerrit

commit 2177468836000ebac3c15ba12dfa69235c8812f2
Author: Antonio Borneo <borneo.antonio@gmail.com>
Date:   Mon May 6 18:16:17 2019 +0200

    coding style: fix space separation
    
    The checkpatch script from Linux kernel v5.1 complains about using
    space before comma, before semicolon and between function name and
    open parenthesis.
    Fix them!
    
    Issue identified using the command
    
    	find src/ -type f -exec ./tools/scripts/checkpatch.pl \
    	-q --types SPACING -f {} \;
    
    The patch only changes amount and position of whitespace, thus
    the following commands show empty diff
    	git diff -w
    	git log -w -p
    	git log -w --stat
    
    Change-Id: I1062051d7f97d59922847f5061c6d6811742d30e
    Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index c9ffa65..922aaf7 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -1923,7 +1923,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
 			.pChip  = NULL,
 			.pBank  = NULL,
 			.bank_number = 1,
-			.base_address = FLASH_BANK1_BASE_512K_AX ,
+			.base_address = FLASH_BANK1_BASE_512K_AX,
 			.controller_address = 0x400e0c00,
 			.flash_wait_states = 6,	/* workaround silicon bug */
 			.present = 1,
diff --git a/src/flash/nor/fespi.c b/src/flash/nor/fespi.c
index 90242b1..7943504 100644
--- a/src/flash/nor/fespi.c
+++ b/src/flash/nor/fespi.c
@@ -136,7 +136,7 @@ struct fespi_target {
 /* TODO !!! What is the right naming convention here? */
 static const struct fespi_target target_devices[] = {
 	/* name,   tap_idcode, ctrl_base */
-	{ "Freedom E300 SPI Flash",  0x10e31913 , 0x10014000 },
+	{ "Freedom E300 SPI Flash", 0x10e31913, 0x10014000 },
 	{ NULL,    0,           0          }
 };
 
diff --git a/src/flash/nor/lpcspifi.c b/src/flash/nor/lpcspifi.c
index 04ac3bb..c4b1037 100644
--- a/src/flash/nor/lpcspifi.c
+++ b/src/flash/nor/lpcspifi.c
@@ -216,7 +216,7 @@ static int lpcspifi_set_hw_mode(struct flash_bank *bank)
 
 	/* Run the algorithm */
 	LOG_DEBUG("Running SPIFI init algorithm");
-	retval = target_run_algorithm(target, 0 , NULL, 2, reg_params,
+	retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 		spifi_init_algorithm->address,
 		spifi_init_algorithm->address + sizeof(spifi_init_code) - 2,
 		1000, &armv7m_info);
@@ -550,7 +550,7 @@ static int lpcspifi_erase(struct flash_bank *bank, int first, int \
last)  buf_set_u32(reg_params[3].value, 0, 32, bank->sectors[first].size);
 
 	/* Run the algorithm */
-	retval = target_run_algorithm(target, 0 , NULL, 4, reg_params,
+	retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
 		erase_algorithm->address,
 		erase_algorithm->address + sizeof(lpcspifi_flash_erase_code) - 4,
 		3000*(last - first + 1), &armv7m_info);
diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c
index 7b67bb8..9824a46 100644
--- a/src/flash/nor/niietcm4.c
+++ b/src/flash/nor/niietcm4.c
@@ -1656,7 +1656,7 @@ static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
 				niietcm4_info->extmem_boot_pin,
 				niietcm4_info->extmem_boot_altfunc,
 				niietcm4_info->extmem_boot ? "enable" : "disable");
-	} else{
+	} else {
 		bank->size = 0x100000;
 		bank->num_sectors = 128;
 
diff --git a/src/flash/nor/numicro.c b/src/flash/nor/numicro.c
index a485282..69f2109 100644
--- a/src/flash/nor/numicro.c
+++ b/src/flash/nor/numicro.c
@@ -694,80 +694,80 @@ static const struct numicro_cpu_type NuMicroParts[] = {
 
 
 	/* M052 */
-	{"M052LAN"  , 0x00005200, NUMICRO_BANKS_M051(8*1024)},
-	{"M052PAN"  , 0x00005201, NUMICRO_BANKS_M051(8*1024)},
-	{"M052YAN"  , 0x00005202, NUMICRO_BANKS_M051(8*1024)},
-	{"M052ZAN"  , 0x00005203, NUMICRO_BANKS_M051(8*1024)},
+	{"M052LAN",   0x00005200, NUMICRO_BANKS_M051(8*1024)},
+	{"M052PAN",   0x00005201, NUMICRO_BANKS_M051(8*1024)},
+	{"M052YAN",   0x00005202, NUMICRO_BANKS_M051(8*1024)},
+	{"M052ZAN",   0x00005203, NUMICRO_BANKS_M051(8*1024)},
 
     /* M054 */
-	{"M054LAN"  , 0x00005400, NUMICRO_BANKS_M051(16*1024)},
-	{"M054PAN"  , 0x00005401, NUMICRO_BANKS_M051(16*1024)},
-	{"M054YAN"  , 0x00005402, NUMICRO_BANKS_M051(16*1024)},
-	{"M054ZAN"  , 0x00005403, NUMICRO_BANKS_M051(16*1024)},
+	{"M054LAN",   0x00005400, NUMICRO_BANKS_M051(16*1024)},
+	{"M054PAN",   0x00005401, NUMICRO_BANKS_M051(16*1024)},
+	{"M054YAN",   0x00005402, NUMICRO_BANKS_M051(16*1024)},
+	{"M054ZAN",   0x00005403, NUMICRO_BANKS_M051(16*1024)},
 
     /* M058 */
-	{"M058LAN"  , 0x00005800, NUMICRO_BANKS_M051(32*1024)},
-	{"M058PAN"  , 0x00005801, NUMICRO_BANKS_M051(32*1024)},
-	{"M058YAN"  , 0x00005802, NUMICRO_BANKS_M051(32*1024)},
-	{"M058ZAN"  , 0x00005803, NUMICRO_BANKS_M051(32*1024)},
+	{"M058LAN",   0x00005800, NUMICRO_BANKS_M051(32*1024)},
+	{"M058PAN",   0x00005801, NUMICRO_BANKS_M051(32*1024)},
+	{"M058YAN",   0x00005802, NUMICRO_BANKS_M051(32*1024)},
+	{"M058ZAN",   0x00005803, NUMICRO_BANKS_M051(32*1024)},
 
     /* M0516 */
-	{"M0516LAN" , 0x00005A00, NUMICRO_BANKS_M051(64*1024)},
-	{"M0516PAN" , 0x00005A01, NUMICRO_BANKS_M051(64*1024)},
-	{"M0516YAN" , 0x00005A02, NUMICRO_BANKS_M051(64*1024)},
-	{"M0516ZAN" , 0x00005A03, NUMICRO_BANKS_M051(64*1024)},
-	{"M051LBN"  , 0x10005100, NUMICRO_BANKS_M051(4*1024)},
-	{"M051PBN"  , 0x10005101, NUMICRO_BANKS_M051(4*1024)},
-	{"M051YBN"  , 0x10005102, NUMICRO_BANKS_M051(4*1024)},
-	{"M051ZBN"  , 0x10005103, NUMICRO_BANKS_M051(4*1024)},
-	{"M052LBN"  , 0x10005200, NUMICRO_BANKS_M051(8*1024)},
-	{"M052PBN"  , 0x10005201, NUMICRO_BANKS_M051(8*1024)},
-	{"M052YBN"  , 0x10005202, NUMICRO_BANKS_M051(8*1024)},
-	{"M052ZBN"  , 0x10005203, NUMICRO_BANKS_M051(8*1024)},
-	{"M054LBN"  , 0x10005400, NUMICRO_BANKS_M051(16*1024)},
-	{"M054PBN"  , 0x10005401, NUMICRO_BANKS_M051(16*1024)},
-	{"M054YBN"  , 0x10005402, NUMICRO_BANKS_M051(16*1024)},
-	{"M054ZBN"  , 0x10005403, NUMICRO_BANKS_M051(16*1024)},
-	{"M058LBN"  , 0x10005800, NUMICRO_BANKS_M051(32*1024)},
-	{"M058PBN"  , 0x10005801, NUMICRO_BANKS_M051(32*1024)},
-	{"M058YBN"  , 0x10005802, NUMICRO_BANKS_M051(32*1024)},
-	{"M058ZBN"  , 0x10005803, NUMICRO_BANKS_M051(32*1024)},
-	{"M0516LBN" , 0x10005A00, NUMICRO_BANKS_M051(64*1024)},
-	{"M0516PBN" , 0x10005A01, NUMICRO_BANKS_M051(64*1024)},
-	{"M0516YBN" , 0x10005A02, NUMICRO_BANKS_M051(64*1024)},
-	{"M0516ZBN" , 0x10005A03, NUMICRO_BANKS_M051(64*1024)},
-	{"M052LDN"  , 0x20005200, NUMICRO_BANKS_M051(8*1024)},
-	{"M054LDN"  , 0x20005400, NUMICRO_BANKS_M051(16*1024)},
-	{"M058LDN"  , 0x20005800, NUMICRO_BANKS_M051(32*1024)},
-	{"M0516LDN" , 0x20005A00, NUMICRO_BANKS_M051(64*1024)},
-	{"M052ZDN"  , 0x20005203, NUMICRO_BANKS_M051(8*1024)},
-	{"M054ZDN"  , 0x20005403, NUMICRO_BANKS_M051(16*1024)},
-	{"M058ZDN"  , 0x20005803, NUMICRO_BANKS_M051(32*1024)},
-	{"M0516ZDN" , 0x20005A03, NUMICRO_BANKS_M051(64*1024)},
-	{"M052TDN"  , 0x20005204, NUMICRO_BANKS_M051(8*1024)},
-	{"M054TDN"  , 0x20005404, NUMICRO_BANKS_M051(16*1024)},
-	{"M058TDN"  , 0x20005804, NUMICRO_BANKS_M051(32*1024)},
-	{"M0516TDN" , 0x20005A04, NUMICRO_BANKS_M051(64*1024)},
-	{"M052XDN"  , 0x20005205, NUMICRO_BANKS_M051(8*1024)},
-	{"M054XDN"  , 0x20005405, NUMICRO_BANKS_M051(16*1024)},
-	{"M058XDN"  , 0x20005805, NUMICRO_BANKS_M051(32*1024)},
-	{"M0516XDN" , 0x20005A05, NUMICRO_BANKS_M051(64*1024)},
-	{"M052LDE"  , 0x30005200, NUMICRO_BANKS_M051(8*1024)},
-	{"M054LDE"  , 0x30005400, NUMICRO_BANKS_M051(16*1024)},
-	{"M058LDE"  , 0x30005800, NUMICRO_BANKS_M051(32*1024)},
-	{"M0516LDE" , 0x30005A00, NUMICRO_BANKS_M051(64*1024)},
-	{"M052ZDE"  , 0x30005203, NUMICRO_BANKS_M051(8*1024)},
-	{"M054ZDE"  , 0x30005403, NUMICRO_BANKS_M051(16*1024)},
-	{"M058ZDE"  , 0x30005803, NUMICRO_BANKS_M051(32*1024)},
-	{"M0516ZDE" , 0x30005A03, NUMICRO_BANKS_M051(64*1024)},
-	{"M052TDE"  , 0x30005204, NUMICRO_BANKS_M051(8*1024)},
-	{"M054TDE"  , 0x30005404, NUMICRO_BANKS_M051(16*1024)},
-	{"M058TDE"  , 0x30005804, NUMICRO_BANKS_M051(32*1024)},
-	{"M0516TDE" , 0x30005A04, NUMICRO_BANKS_M051(64*1024)},
-	{"M052XDE"  , 0x30005205, NUMICRO_BANKS_M051(8*1024)},
-	{"M054XDE"  , 0x30005405, NUMICRO_BANKS_M051(16*1024)},
-	{"M058XDE"  , 0x30005805, NUMICRO_BANKS_M051(32*1024)},
-	{"M0516XDE" , 0x30005A05, NUMICRO_BANKS_M051(64*1024)},
+	{"M0516LAN",  0x00005A00, NUMICRO_BANKS_M051(64*1024)},
+	{"M0516PAN",  0x00005A01, NUMICRO_BANKS_M051(64*1024)},
+	{"M0516YAN",  0x00005A02, NUMICRO_BANKS_M051(64*1024)},
+	{"M0516ZAN",  0x00005A03, NUMICRO_BANKS_M051(64*1024)},
+	{"M051LBN",   0x10005100, NUMICRO_BANKS_M051(4*1024)},
+	{"M051PBN",   0x10005101, NUMICRO_BANKS_M051(4*1024)},
+	{"M051YBN",   0x10005102, NUMICRO_BANKS_M051(4*1024)},
+	{"M051ZBN",   0x10005103, NUMICRO_BANKS_M051(4*1024)},
+	{"M052LBN",   0x10005200, NUMICRO_BANKS_M051(8*1024)},
+	{"M052PBN",   0x10005201, NUMICRO_BANKS_M051(8*1024)},
+	{"M052YBN",   0x10005202, NUMICRO_BANKS_M051(8*1024)},
+	{"M052ZBN",   0x10005203, NUMICRO_BANKS_M051(8*1024)},
+	{"M054LBN",   0x10005400, NUMICRO_BANKS_M051(16*1024)},
+	{"M054PBN",   0x10005401, NUMICRO_BANKS_M051(16*1024)},
+	{"M054YBN",   0x10005402, NUMICRO_BANKS_M051(16*1024)},
+	{"M054ZBN",   0x10005403, NUMICRO_BANKS_M051(16*1024)},
+	{"M058LBN",   0x10005800, NUMICRO_BANKS_M051(32*1024)},
+	{"M058PBN",   0x10005801, NUMICRO_BANKS_M051(32*1024)},
+	{"M058YBN",   0x10005802, NUMICRO_BANKS_M051(32*1024)},
+	{"M058ZBN",   0x10005803, NUMICRO_BANKS_M051(32*1024)},
+	{"M0516LBN",  0x10005A00, NUMICRO_BANKS_M051(64*1024)},
+	{"M0516PBN",  0x10005A01, NUMICRO_BANKS_M051(64*1024)},
+	{"M0516YBN",  0x10005A02, NUMICRO_BANKS_M051(64*1024)},
+	{"M0516ZBN",  0x10005A03, NUMICRO_BANKS_M051(64*1024)},
+	{"M052LDN",   0x20005200, NUMICRO_BANKS_M051(8*1024)},
+	{"M054LDN",   0x20005400, NUMICRO_BANKS_M051(16*1024)},
+	{"M058LDN",   0x20005800, NUMICRO_BANKS_M051(32*1024)},
+	{"M0516LDN",  0x20005A00, NUMICRO_BANKS_M051(64*1024)},
+	{"M052ZDN",   0x20005203, NUMICRO_BANKS_M051(8*1024)},
+	{"M054ZDN",   0x20005403, NUMICRO_BANKS_M051(16*1024)},
+	{"M058ZDN",   0x20005803, NUMICRO_BANKS_M051(32*1024)},
+	{"M0516ZDN",  0x20005A03, NUMICRO_BANKS_M051(64*1024)},
+	{"M052TDN",   0x20005204, NUMICRO_BANKS_M051(8*1024)},
+	{"M054TDN",   0x20005404, NUMICRO_BANKS_M051(16*1024)},
+	{"M058TDN",   0x20005804, NUMICRO_BANKS_M051(32*1024)},
+	{"M0516TDN",  0x20005A04, NUMICRO_BANKS_M051(64*1024)},
+	{"M052XDN",   0x20005205, NUMICRO_BANKS_M051(8*1024)},
+	{"M054XDN",   0x20005405, NUMICRO_BANKS_M051(16*1024)},
+	{"M058XDN",   0x20005805, NUMICRO_BANKS_M051(32*1024)},
+	{"M0516XDN",  0x20005A05, NUMICRO_BANKS_M051(64*1024)},
+	{"M052LDE",   0x30005200, NUMICRO_BANKS_M051(8*1024)},
+	{"M054LDE",   0x30005400, NUMICRO_BANKS_M051(16*1024)},
+	{"M058LDE",   0x30005800, NUMICRO_BANKS_M051(32*1024)},
+	{"M0516LDE",  0x30005A00, NUMICRO_BANKS_M051(64*1024)},
+	{"M052ZDE",   0x30005203, NUMICRO_BANKS_M051(8*1024)},
+	{"M054ZDE",   0x30005403, NUMICRO_BANKS_M051(16*1024)},
+	{"M058ZDE",   0x30005803, NUMICRO_BANKS_M051(32*1024)},
+	{"M0516ZDE",  0x30005A03, NUMICRO_BANKS_M051(64*1024)},
+	{"M052TDE",   0x30005204, NUMICRO_BANKS_M051(8*1024)},
+	{"M054TDE",   0x30005404, NUMICRO_BANKS_M051(16*1024)},
+	{"M058TDE",   0x30005804, NUMICRO_BANKS_M051(32*1024)},
+	{"M0516TDE",  0x30005A04, NUMICRO_BANKS_M051(64*1024)},
+	{"M052XDE",   0x30005205, NUMICRO_BANKS_M051(8*1024)},
+	{"M054XDE",   0x30005405, NUMICRO_BANKS_M051(16*1024)},
+	{"M058XDE",   0x30005805, NUMICRO_BANKS_M051(32*1024)},
+	{"M0516XDE",  0x30005A05, NUMICRO_BANKS_M051(64*1024)},
 
 	/* Mini51 */
 	{"MINI51LAN",  0x00205100, NUMICRO_BANKS_MINI51(4*1024)},
@@ -798,335 +798,335 @@ static const struct numicro_cpu_type NuMicroParts[] = {
 	{"MINI54LBN",  0x10205400, NUMICRO_BANKS_MINI51(16*1024)},
 	{"MINI54QBN",  0x10205401, NUMICRO_BANKS_MINI51(16*1024)},
 	{"MINI54   ",  0x10205402, NUMICRO_BANKS_MINI51(16*1024)},
-	{"MINI54ZBN" , 0x10205403, NUMICRO_BANKS_MINI51(16*1024)},
-	{"MINI54TBN" , 0x10205404, NUMICRO_BANKS_MINI51(16*1024)},
-	{"MINI51LDE" , 0x20205100, NUMICRO_BANKS_MINI51(4*1024)},
-	{"MINI51QDE" , 0x20205101, NUMICRO_BANKS_MINI51(4*1024)},
-	{"MINI51   " , 0x20205102, NUMICRO_BANKS_MINI51(4*1024)},
-	{"MINI51ZDE" , 0x20205103, NUMICRO_BANKS_MINI51(4*1024)},
-	{"MINI51TDE" , 0x20205104, NUMICRO_BANKS_MINI51(4*1024)},
-	{"MINI51FDE" , 0x20205105, NUMICRO_BANKS_MINI51(4*1024)},
-	{"MINI52LDE" , 0x20205200, NUMICRO_BANKS_MINI51(8*1024)},
-	{"MINI52QDE" , 0x20205201, NUMICRO_BANKS_MINI51(8*1024)},
-	{"MINI52   " , 0x20205202, NUMICRO_BANKS_MINI51(8*1024)},
-	{"MINI52ZDE" , 0x20205203, NUMICRO_BANKS_MINI51(8*1024)},
-	{"MINI52TDE" , 0x20205204, NUMICRO_BANKS_MINI51(8*1024)},
-	{"MINI52FDE" , 0x20205205, NUMICRO_BANKS_MINI51(8*1024)},
-	{"MINI54LDE" , 0x20205400, NUMICRO_BANKS_MINI51(16*1024)},
-	{"MINI54QDE" , 0x20205401, NUMICRO_BANKS_MINI51(16*1024)},
-	{"MINI54   " , 0x20205402, NUMICRO_BANKS_MINI51(16*1024)},
-	{"MINI54ZDE" , 0x20205403, NUMICRO_BANKS_MINI51(16*1024)},
-	{"MINI54TDE" , 0x20205404, NUMICRO_BANKS_MINI51(16*1024)},
-	{"MINI54FDE" , 0x20205405, NUMICRO_BANKS_MINI51(16*1024)},
-	{"MINI55LDE" , 0x20205500, NUMICRO_BANKS_MINI51(16*1024)},
+	{"MINI54ZBN",  0x10205403, NUMICRO_BANKS_MINI51(16*1024)},
+	{"MINI54TBN",  0x10205404, NUMICRO_BANKS_MINI51(16*1024)},
+	{"MINI51LDE",  0x20205100, NUMICRO_BANKS_MINI51(4*1024)},
+	{"MINI51QDE",  0x20205101, NUMICRO_BANKS_MINI51(4*1024)},
+	{"MINI51   ",  0x20205102, NUMICRO_BANKS_MINI51(4*1024)},
+	{"MINI51ZDE",  0x20205103, NUMICRO_BANKS_MINI51(4*1024)},
+	{"MINI51TDE",  0x20205104, NUMICRO_BANKS_MINI51(4*1024)},
+	{"MINI51FDE",  0x20205105, NUMICRO_BANKS_MINI51(4*1024)},
+	{"MINI52LDE",  0x20205200, NUMICRO_BANKS_MINI51(8*1024)},
+	{"MINI52QDE",  0x20205201, NUMICRO_BANKS_MINI51(8*1024)},
+	{"MINI52   ",  0x20205202, NUMICRO_BANKS_MINI51(8*1024)},
+	{"MINI52ZDE",  0x20205203, NUMICRO_BANKS_MINI51(8*1024)},
+	{"MINI52TDE",  0x20205204, NUMICRO_BANKS_MINI51(8*1024)},
+	{"MINI52FDE",  0x20205205, NUMICRO_BANKS_MINI51(8*1024)},
+	{"MINI54LDE",  0x20205400, NUMICRO_BANKS_MINI51(16*1024)},
+	{"MINI54QDE",  0x20205401, NUMICRO_BANKS_MINI51(16*1024)},
+	{"MINI54   ",  0x20205402, NUMICRO_BANKS_MINI51(16*1024)},
+	{"MINI54ZDE",  0x20205403, NUMICRO_BANKS_MINI51(16*1024)},
+	{"MINI54TDE",  0x20205404, NUMICRO_BANKS_MINI51(16*1024)},
+	{"MINI54FDE",  0x20205405, NUMICRO_BANKS_MINI51(16*1024)},
+	{"MINI55LDE",  0x20205500, NUMICRO_BANKS_MINI51(16*1024)},
 
 	/* NANO100 */
-	{"NANO100VF3AN" , 0x00110000, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO100VF2AN" , 0x00110001, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO100RF3AN" , 0x00110002, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO100RF2AN" , 0x00110003, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO100LF3AN" , 0x00110004, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO100LF2AN" , 0x00110005, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO100VE3AN" , 0x00110006, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100VE2AN" , 0x00110007, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100RE3AN" , 0x00110008, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100RE2AN" , 0x00110009, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100LE3AN" , 0x00110010, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100LE2AN" , 0x00110011, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100VD3AN" , 0x00110012, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100VD2AN" , 0x00110013, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100VD1AN" , 0x00110014, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100RD3AN" , 0x00110015, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100RD2AN" , 0x00110016, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100RD1AN" , 0x00110017, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100LD3AN" , 0x00110018, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100LD2AN" , 0x00110019, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100LD1AN" , 0x00110020, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100VC2AN" , 0x00110021, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO100VC1AN" , 0x00110022, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO100RC2AN" , 0x00110023, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO100RC1AN" , 0x00110024, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO100LC2AN" , 0x00110025, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO100LC1AN" , 0x00110026, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO100VB1AN" , 0x00110027, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO100VB0AN" , 0x00110028, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO100RB1AN" , 0x00110029, NUMICRO_BANKS_NANO(16*1024)},
-
-	{"NANO110VF3AN" , 0x00111000, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO110VF2AN" , 0x00111001, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO110RF3AN" , 0x00111002, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO110RF2AN" , 0x00111003, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO110VE3AN" , 0x00111006, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110VE2AN" , 0x00111007, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110RE3AN" , 0x00111008, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110RE2AN" , 0x00111009, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110VD3AN" , 0x00111012, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110VD2AN" , 0x00111013, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110VD1AN" , 0x00111014, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110RD3AN" , 0x00111015, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110RD2AN" , 0x00111016, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110RD1AN" , 0x00111017, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110VC2AN" , 0x00111021, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO110VC1AN" , 0x00111022, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO110SC2AN" , 0x00111023, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO110SC1AN" , 0x00111024, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO120VF3AN" , 0x00112000, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO120VF2AN" , 0x00112001, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO120RF3AN" , 0x00112002, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO120RF2AN" , 0x00112003, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO120LF3AN" , 0x00112004, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO120LF2AN" , 0x00112005, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO120VE3AN" , 0x00112006, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120VE2AN" , 0x00112007, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120RE3AN" , 0x00112008, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120RE2AN" , 0x00112009, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120LE3AN" , 0x00112010, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120LE2AN" , 0x00112011, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120VD3AN" , 0x00112012, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120VD2AN" , 0x00112013, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120VD1AN" , 0x00112014, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120SD3AN" , 0x00112015, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120SD2AN" , 0x00112016, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120SD1AN" , 0x00112017, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120LD3AN" , 0x00112018, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120LD2AN" , 0x00112019, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120LD1AN" , 0x00112020, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120VC2AN" , 0x00112021, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO120VC1AN" , 0x00112022, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO120SC2AN" , 0x00112023, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO120SC1AN" , 0x00112024, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO120LC2AN" , 0x00112025, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO120LC1AN" , 0x00112026, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO130VF3AN" , 0x00113000, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO130VF2AN" , 0x00113001, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO130SF3AN" , 0x00113002, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO130SF2AN" , 0x00113003, NUMICRO_BANKS_NANO(256*1024)},
-	{"NANO130VE3AN" , 0x00113006, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO130VE2AN" , 0x00113007, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO130SE3AN" , 0x00113008, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO130SE2AN" , 0x00113009, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO130VD3AN" , 0x00113012, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130VD2AN" , 0x00113013, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130VD1AN" , 0x00113014, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130SD3AN" , 0x00113015, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130SD2AN" , 0x00113016, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130SD1AN" , 0x00113017, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130VC2AN" , 0x00113021, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO130VC1AN" , 0x00113022, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO130SC2AN" , 0x00113023, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO130SC1AN" , 0x00113024, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO100KE3BN" , 0x00110030, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100KE2BN" , 0x00110031, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100VE3BN" , 0x00110032, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100VE2BN" , 0x00110033, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100SE3BN" , 0x00110034, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100SE2BN" , 0x00110035, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100LE3BN" , 0x00110036, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100LE2BN" , 0x00110037, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO100KD3BN" , 0x00110038, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100KD2BN" , 0x00110039, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100VD3BN" , 0x0011003A, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100VD2BN" , 0x0011003B, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100SD3BN" , 0x0011003C, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100SD2BN" , 0x0011003D, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100LD3BN" , 0x0011003E, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100LD2BN" , 0x0011003F, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO100KC2BN" , 0x00110040, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO100VC2BN" , 0x00110041, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO100SC2BN" , 0x00110042, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO100LC2BN" , 0x00110043, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO110KE3BN" , 0x00111030, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110KE2BN" , 0x00111031, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110VE3BN" , 0x00111032, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110VE2BN" , 0x00111033, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110SE3BN" , 0x00111034, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110SE2BN" , 0x00111035, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110KD3BN" , 0x00111038, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110KD2BN" , 0x00111039, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110VD3BN" , 0x0011103A, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110VD2BN" , 0x0011103B, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110SD3BN" , 0x0011103C, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110SD2BN" , 0x0011103D, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO110KC2BN" , 0x00111040, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO110VC2BN" , 0x00111041, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO110SC2BN" , 0x00111042, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO120KE3BN" , 0x00112030, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120KE2BN" , 0x00112031, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120VE3BN" , 0x00112032, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120VE2BN" , 0x00112033, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120SE3BN" , 0x00112034, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120SE2BN" , 0x00112035, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120LE3BN" , 0x00112036, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120LE2BN" , 0x00112037, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO120KD3BN" , 0x00112038, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120KD2BN" , 0x00112039, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120VD3BN" , 0x0011203A, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120VD2BN" , 0x0011203B, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120SD3BN" , 0x0011203C, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120SD2BN" , 0x0011203D, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120LD3BN" , 0x0011203E, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120LD2BN" , 0x0011203F, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO120KC2BN" , 0x00112040, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO120VC2BN" , 0x00112041, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO120SC2BN" , 0x00112042, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO120LC2BN" , 0x00112043, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO130KE3BN" , 0x00113030, NUMICRO_BANKS_NANO(123*1024)},
-	{"NANO130KE2BN" , 0x00113031, NUMICRO_BANKS_NANO(123*1024)},
-	{"NANO130VE3BN" , 0x00113032, NUMICRO_BANKS_NANO(123*1024)},
-	{"NANO130VE2BN" , 0x00113033, NUMICRO_BANKS_NANO(123*1024)},
-	{"NANO130SE3BN" , 0x00113034, NUMICRO_BANKS_NANO(123*1024)},
-	{"NANO130SE2BN" , 0x00113035, NUMICRO_BANKS_NANO(123*1024)},
-	{"NANO130KD3BN" , 0x00113038, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130KD2BN" , 0x00113039, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130VD3BN" , 0x0011303A, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130VD2BN" , 0x0011303B, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130SD3BN" , 0x0011303C, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130SD2BN" , 0x0011303D, NUMICRO_BANKS_NANO(64*1024)},
-	{"NANO130KC2BN" , 0x00113040, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO130VC2BN" , 0x00113041, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO130SC2BN" , 0x00113042, NUMICRO_BANKS_NANO(32*1024)},
-	{"N512DC4"      , 0x00100000, NUMICRO_BANKS_NANO(64*1024)},
-	{"N512LC4"      , 0x00100001, NUMICRO_BANKS_NANO(64*1024)},
-	{"N512MC4"      , 0x00100003, NUMICRO_BANKS_NANO(64*1024)},
-
-	{"N512SC4"      , 0x00100005, NUMICRO_BANKS_NANO(64*1024)},
-	{"N512VD4"      , 0x00100008, NUMICRO_BANKS_NANO(128*1024)},
-	{"N512MD4"      , 0x00100009, NUMICRO_BANKS_NANO(128*1024)},
-	{"N512SD4"      , 0x00100010, NUMICRO_BANKS_NANO(128*1024)},
-	{"NANO110RC2BN" , 0x00111043, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO110RD3BN" , 0x00111045, NUMICRO_BANKS_NANO(64*1024)},
-	{"TX110VE3BN"   , 0x00111036, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100VF3AN",  0x00110000, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO100VF2AN",  0x00110001, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO100RF3AN",  0x00110002, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO100RF2AN",  0x00110003, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO100LF3AN",  0x00110004, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO100LF2AN",  0x00110005, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO100VE3AN",  0x00110006, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100VE2AN",  0x00110007, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100RE3AN",  0x00110008, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100RE2AN",  0x00110009, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100LE3AN",  0x00110010, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100LE2AN",  0x00110011, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100VD3AN",  0x00110012, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100VD2AN",  0x00110013, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100VD1AN",  0x00110014, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100RD3AN",  0x00110015, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100RD2AN",  0x00110016, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100RD1AN",  0x00110017, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100LD3AN",  0x00110018, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100LD2AN",  0x00110019, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100LD1AN",  0x00110020, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100VC2AN",  0x00110021, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO100VC1AN",  0x00110022, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO100RC2AN",  0x00110023, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO100RC1AN",  0x00110024, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO100LC2AN",  0x00110025, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO100LC1AN",  0x00110026, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO100VB1AN",  0x00110027, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO100VB0AN",  0x00110028, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO100RB1AN",  0x00110029, NUMICRO_BANKS_NANO(16*1024)},
+
+	{"NANO110VF3AN",  0x00111000, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO110VF2AN",  0x00111001, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO110RF3AN",  0x00111002, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO110RF2AN",  0x00111003, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO110VE3AN",  0x00111006, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110VE2AN",  0x00111007, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110RE3AN",  0x00111008, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110RE2AN",  0x00111009, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110VD3AN",  0x00111012, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110VD2AN",  0x00111013, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110VD1AN",  0x00111014, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110RD3AN",  0x00111015, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110RD2AN",  0x00111016, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110RD1AN",  0x00111017, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110VC2AN",  0x00111021, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO110VC1AN",  0x00111022, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO110SC2AN",  0x00111023, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO110SC1AN",  0x00111024, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO120VF3AN",  0x00112000, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO120VF2AN",  0x00112001, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO120RF3AN",  0x00112002, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO120RF2AN",  0x00112003, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO120LF3AN",  0x00112004, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO120LF2AN",  0x00112005, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO120VE3AN",  0x00112006, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120VE2AN",  0x00112007, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120RE3AN",  0x00112008, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120RE2AN",  0x00112009, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120LE3AN",  0x00112010, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120LE2AN",  0x00112011, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120VD3AN",  0x00112012, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120VD2AN",  0x00112013, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120VD1AN",  0x00112014, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120SD3AN",  0x00112015, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120SD2AN",  0x00112016, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120SD1AN",  0x00112017, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120LD3AN",  0x00112018, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120LD2AN",  0x00112019, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120LD1AN",  0x00112020, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120VC2AN",  0x00112021, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO120VC1AN",  0x00112022, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO120SC2AN",  0x00112023, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO120SC1AN",  0x00112024, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO120LC2AN",  0x00112025, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO120LC1AN",  0x00112026, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO130VF3AN",  0x00113000, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO130VF2AN",  0x00113001, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO130SF3AN",  0x00113002, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO130SF2AN",  0x00113003, NUMICRO_BANKS_NANO(256*1024)},
+	{"NANO130VE3AN",  0x00113006, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO130VE2AN",  0x00113007, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO130SE3AN",  0x00113008, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO130SE2AN",  0x00113009, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO130VD3AN",  0x00113012, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130VD2AN",  0x00113013, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130VD1AN",  0x00113014, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130SD3AN",  0x00113015, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130SD2AN",  0x00113016, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130SD1AN",  0x00113017, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130VC2AN",  0x00113021, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO130VC1AN",  0x00113022, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO130SC2AN",  0x00113023, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO130SC1AN",  0x00113024, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO100KE3BN",  0x00110030, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100KE2BN",  0x00110031, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100VE3BN",  0x00110032, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100VE2BN",  0x00110033, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100SE3BN",  0x00110034, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100SE2BN",  0x00110035, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100LE3BN",  0x00110036, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100LE2BN",  0x00110037, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO100KD3BN",  0x00110038, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100KD2BN",  0x00110039, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100VD3BN",  0x0011003A, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100VD2BN",  0x0011003B, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100SD3BN",  0x0011003C, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100SD2BN",  0x0011003D, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100LD3BN",  0x0011003E, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100LD2BN",  0x0011003F, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO100KC2BN",  0x00110040, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO100VC2BN",  0x00110041, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO100SC2BN",  0x00110042, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO100LC2BN",  0x00110043, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO110KE3BN",  0x00111030, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110KE2BN",  0x00111031, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110VE3BN",  0x00111032, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110VE2BN",  0x00111033, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110SE3BN",  0x00111034, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110SE2BN",  0x00111035, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110KD3BN",  0x00111038, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110KD2BN",  0x00111039, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110VD3BN",  0x0011103A, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110VD2BN",  0x0011103B, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110SD3BN",  0x0011103C, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110SD2BN",  0x0011103D, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO110KC2BN",  0x00111040, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO110VC2BN",  0x00111041, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO110SC2BN",  0x00111042, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO120KE3BN",  0x00112030, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120KE2BN",  0x00112031, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120VE3BN",  0x00112032, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120VE2BN",  0x00112033, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120SE3BN",  0x00112034, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120SE2BN",  0x00112035, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120LE3BN",  0x00112036, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120LE2BN",  0x00112037, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO120KD3BN",  0x00112038, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120KD2BN",  0x00112039, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120VD3BN",  0x0011203A, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120VD2BN",  0x0011203B, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120SD3BN",  0x0011203C, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120SD2BN",  0x0011203D, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120LD3BN",  0x0011203E, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120LD2BN",  0x0011203F, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO120KC2BN",  0x00112040, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO120VC2BN",  0x00112041, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO120SC2BN",  0x00112042, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO120LC2BN",  0x00112043, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO130KE3BN",  0x00113030, NUMICRO_BANKS_NANO(123*1024)},
+	{"NANO130KE2BN",  0x00113031, NUMICRO_BANKS_NANO(123*1024)},
+	{"NANO130VE3BN",  0x00113032, NUMICRO_BANKS_NANO(123*1024)},
+	{"NANO130VE2BN",  0x00113033, NUMICRO_BANKS_NANO(123*1024)},
+	{"NANO130SE3BN",  0x00113034, NUMICRO_BANKS_NANO(123*1024)},
+	{"NANO130SE2BN",  0x00113035, NUMICRO_BANKS_NANO(123*1024)},
+	{"NANO130KD3BN",  0x00113038, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130KD2BN",  0x00113039, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130VD3BN",  0x0011303A, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130VD2BN",  0x0011303B, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130SD3BN",  0x0011303C, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130SD2BN",  0x0011303D, NUMICRO_BANKS_NANO(64*1024)},
+	{"NANO130KC2BN",  0x00113040, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO130VC2BN",  0x00113041, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO130SC2BN",  0x00113042, NUMICRO_BANKS_NANO(32*1024)},
+	{"N512DC4",       0x00100000, NUMICRO_BANKS_NANO(64*1024)},
+	{"N512LC4",       0x00100001, NUMICRO_BANKS_NANO(64*1024)},
+	{"N512MC4",       0x00100003, NUMICRO_BANKS_NANO(64*1024)},
+
+	{"N512SC4",       0x00100005, NUMICRO_BANKS_NANO(64*1024)},
+	{"N512VD4",       0x00100008, NUMICRO_BANKS_NANO(128*1024)},
+	{"N512MD4",       0x00100009, NUMICRO_BANKS_NANO(128*1024)},
+	{"N512SD4",       0x00100010, NUMICRO_BANKS_NANO(128*1024)},
+	{"NANO110RC2BN",  0x00111043, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO110RD3BN",  0x00111045, NUMICRO_BANKS_NANO(64*1024)},
+	{"TX110VE3BN",    0x00111036, NUMICRO_BANKS_NANO(128*1024)},
 
 	/* NANO102/NANO112 */
-	{"NANO112LB0AN" , 0x00111201, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO112LB1AN" , 0x00111202, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO112LC1AN" , 0x00111203, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO112LC2AN" , 0x00111204, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO112SB0AN" , 0x00111205, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO112SB1AN" , 0x00111206, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO112SC1AN" , 0x00111207, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO112SC2AN" , 0x00111208, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO112RB0AN" , 0x00111209, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO112RB1AN" , 0x00111210, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO112RC1AN" , 0x00111211, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO112RC2AN" , 0x00111212, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO112VB0AN" , 0x00111213, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO112VB1AN" , 0x00111214, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO112VC1AN" , 0x00111215, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO112VC2AN" , 0x00111216, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO102ZB0AN" , 0x00110201, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO102ZB1AN" , 0x00110202, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO102ZC1AN" , 0x00110203, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO102ZC2AN" , 0x00110204, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO102LB0AN" , 0x00110205, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO102LB1AN" , 0x00110206, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO102LC1AN" , 0x00110207, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO102LC2AN" , 0x00110208, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO102SB0AN" , 0x00110209, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO102SB1AN" , 0x00110210, NUMICRO_BANKS_NANO(16*1024)},
-	{"NANO102SC1AN" , 0x00110211, NUMICRO_BANKS_NANO(32*1024)},
-	{"NANO102SC2AN" , 0x00110212, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO112LB0AN",  0x00111201, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO112LB1AN",  0x00111202, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO112LC1AN",  0x00111203, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO112LC2AN",  0x00111204, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO112SB0AN",  0x00111205, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO112SB1AN",  0x00111206, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO112SC1AN",  0x00111207, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO112SC2AN",  0x00111208, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO112RB0AN",  0x00111209, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO112RB1AN",  0x00111210, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO112RC1AN",  0x00111211, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO112RC2AN",  0x00111212, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO112VB0AN",  0x00111213, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO112VB1AN",  0x00111214, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO112VC1AN",  0x00111215, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO112VC2AN",  0x00111216, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO102ZB0AN",  0x00110201, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO102ZB1AN",  0x00110202, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO102ZC1AN",  0x00110203, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO102ZC2AN",  0x00110204, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO102LB0AN",  0x00110205, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO102LB1AN",  0x00110206, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO102LC1AN",  0x00110207, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO102LC2AN",  0x00110208, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO102SB0AN",  0x00110209, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO102SB1AN",  0x00110210, NUMICRO_BANKS_NANO(16*1024)},
+	{"NANO102SC1AN",  0x00110211, NUMICRO_BANKS_NANO(32*1024)},
+	{"NANO102SC2AN",  0x00110212, NUMICRO_BANKS_NANO(32*1024)},
 
 	/* NUC103/NUC105/NUC123 */
-	{"NUC123SC2AN" , 0x00012305, NUMICRO_BANKS_NUC100(36*1024)},
-	{"NUC123SD4AN" , 0x00012315, NUMICRO_BANKS_NUC100(68*1024)},
-	{"NUC123LC2AN" , 0x00012325, NUMICRO_BANKS_NUC100(36*1024)},
-	{"NUC103LC2AN" , 0x00010325, NUMICRO_BANKS_NUC100(36*1024)},
-	{"NUC105LC2AN" , 0x00010525, NUMICRO_BANKS_NUC100(36*1024)},
-	{"NUC123LD4AN" , 0x00012335, NUMICRO_BANKS_NUC100(68*1024)},
-	{"NUC103LD4AN" , 0x00010335, NUMICRO_BANKS_NUC100(68*1024)},
-	{"NUC105LD4AN" , 0x00010535, NUMICRO_BANKS_NUC100(68*1024)},
-	{"NUC123ZC2AN" , 0x00012345, NUMICRO_BANKS_NUC100(36*1024)},
-	{"NUC103ZC2AN" , 0x00010345, NUMICRO_BANKS_NUC100(36*1024)},
-	{"NUC105ZC2AN" , 0x00010545, NUMICRO_BANKS_NUC100(36*1024)},
-	{"NUC123ZD4AN" , 0x00012355, NUMICRO_BANKS_NUC100(68*1024)},
-	{"NUC103ZD4AN" , 0x00010355, NUMICRO_BANKS_NUC100(68*1024)},
-	{"NUC105ZD4AN" , 0x00010555, NUMICRO_BANKS_NUC100(68*1024)},
+	{"NUC123SC2AN",  0x00012305, NUMICRO_BANKS_NUC100(36*1024)},
+	{"NUC123SD4AN",  0x00012315, NUMICRO_BANKS_NUC100(68*1024)},
+	{"NUC123LC2AN",  0x00012325, NUMICRO_BANKS_NUC100(36*1024)},
+	{"NUC103LC2AN",  0x00010325, NUMICRO_BANKS_NUC100(36*1024)},
+	{"NUC105LC2AN",  0x00010525, NUMICRO_BANKS_NUC100(36*1024)},
+	{"NUC123LD4AN",  0x00012335, NUMICRO_BANKS_NUC100(68*1024)},
+	{"NUC103LD4AN",  0x00010335, NUMICRO_BANKS_NUC100(68*1024)},
+	{"NUC105LD4AN",  0x00010535, NUMICRO_BANKS_NUC100(68*1024)},
+	{"NUC123ZC2AN",  0x00012345, NUMICRO_BANKS_NUC100(36*1024)},
+	{"NUC103ZC2AN",  0x00010345, NUMICRO_BANKS_NUC100(36*1024)},
+	{"NUC105ZC2AN",  0x00010545, NUMICRO_BANKS_NUC100(36*1024)},
+	{"NUC123ZD4AN",  0x00012355, NUMICRO_BANKS_NUC100(68*1024)},
+	{"NUC103ZD4AN",  0x00010355, NUMICRO_BANKS_NUC100(68*1024)},
+	{"NUC105ZD4AN",  0x00010555, NUMICRO_BANKS_NUC100(68*1024)},
 
 	/* NUC200 */
-	{"NUC200LC2AN" , 0x00020007, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC200LD2AN" , 0x00020004, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC200LE3AN" , 0x00020000, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC200SC1AN" , 0x00020035, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC200SD2AN" , 0x00020031, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC200SE3AN" , 0x00020027, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC200VE3AN" , 0x00020018, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC220LC2AN" , 0x00022007, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC220LD2AN" , 0x00022004, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC220LE3AN" , 0x00022000, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC220SC1AN" , 0x00022035, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC220SD2AN" , 0x00022031, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC220SE3AN" , 0x00022027, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC220VE3AN" , 0x00022018, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC230LC2AN" , 0x00023007, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC230LD2AN" , 0x00023004, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC230LE3AN" , 0x00023000, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC230SC1AN" , 0x00023035, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC230SD2AN" , 0x00023031, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC230SE3AN" , 0x00023027, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC230VE3AN" , 0x00023018, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC240LC2AN" , 0x00024007, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC240LD2AN" , 0x00024004, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC240LE3AN" , 0x00024000, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC240SC1AN" , 0x00024035, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC240SD2AN" , 0x00024031, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC240SE3AN" , 0x00024027, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC240VE3AN" , 0x00024018, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC200LC2AN",  0x00020007, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC200LD2AN",  0x00020004, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC200LE3AN",  0x00020000, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC200SC1AN",  0x00020035, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC200SD2AN",  0x00020031, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC200SE3AN",  0x00020027, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC200VE3AN",  0x00020018, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC220LC2AN",  0x00022007, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC220LD2AN",  0x00022004, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC220LE3AN",  0x00022000, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC220SC1AN",  0x00022035, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC220SD2AN",  0x00022031, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC220SE3AN",  0x00022027, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC220VE3AN",  0x00022018, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC230LC2AN",  0x00023007, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC230LD2AN",  0x00023004, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC230LE3AN",  0x00023000, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC230SC1AN",  0x00023035, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC230SD2AN",  0x00023031, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC230SE3AN",  0x00023027, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC230VE3AN",  0x00023018, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC240LC2AN",  0x00024007, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC240LD2AN",  0x00024004, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC240LE3AN",  0x00024000, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC240SC1AN",  0x00024035, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC240SD2AN",  0x00024031, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC240SE3AN",  0x00024027, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC240VE3AN",  0x00024018, NUMICRO_BANKS_NUC100(128*1024)},
 
 	/* NUC200 NUC2XXAE */
-	{"NUC230RC1AE" , 0x40013017, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC200LC2AE" , 0x10020007, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC200LD2AE" , 0x10020004, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC200LE3AE" , 0x10020000, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC200SC2AE" , 0x10020034, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC200SD2AE" , 0x10020031, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC200SE3AE" , 0x10020027, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC200VE3AE" , 0x10020018, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC230LC2AE" , 0x10023007, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC230LD2AE" , 0x10023004, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC230LE3AE" , 0x10023000, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC230SC2AE" , 0x10023034, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC230SD2AE" , 0x10023031, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC230SE3AE" , 0x10023027, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC230VE3AE" , 0x10023018, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC240LC2AE" , 0x10024007, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC240LD2AE" , 0x10024004, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC240LE3AE" , 0x10024000, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC240SC2AE" , 0x10024034, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC240SD2AE" , 0x10024031, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC240SE3AE" , 0x10024027, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC240VE3AE" , 0x10024018, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC230RC1AE",  0x40013017, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC200LC2AE",  0x10020007, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC200LD2AE",  0x10020004, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC200LE3AE",  0x10020000, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC200SC2AE",  0x10020034, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC200SD2AE",  0x10020031, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC200SE3AE",  0x10020027, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC200VE3AE",  0x10020018, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC230LC2AE",  0x10023007, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC230LD2AE",  0x10023004, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC230LE3AE",  0x10023000, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC230SC2AE",  0x10023034, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC230SD2AE",  0x10023031, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC230SE3AE",  0x10023027, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC230VE3AE",  0x10023018, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC240LC2AE",  0x10024007, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC240LD2AE",  0x10024004, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC240LE3AE",  0x10024000, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC240SC2AE",  0x10024034, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC240SD2AE",  0x10024031, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC240SE3AE",  0x10024027, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC240VE3AE",  0x10024018, NUMICRO_BANKS_NUC100(128*1024)},
 
 	/* NUC100 Version D */
-	{"NUC100LC1DN" , 0x30010008, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC100LD1DN" , 0x30010005, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC100LD2DN" , 0x30010004, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC100RC1DN" , 0x30010017, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC100RD1DN" , 0x30010014, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC100RD2DN" , 0x30010013, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC100LD3DN" , 0x30010003, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC100LE3DN" , 0x30010000, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC100RD3DN" , 0x30010012, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC100RE3DN" , 0x30010009, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC100VD2DN" , 0x30010022, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC100VD3DN" , 0x30010021, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC100VE3DN" , 0x30010018, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC120LC1DN" , 0x30012008, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC120LD1DN" , 0x30012005, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC120LD2DN" , 0x30012004, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC120RC1DN" , 0x30012017, NUMICRO_BANKS_NUC100(32*1024)},
-	{"NUC120RD1DN" , 0x30012014, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC120RD2DN" , 0x30012013, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC120LD3DN" , 0x30012003, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC120LE3DN" , 0x30012000, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC120RD3DN" , 0x30012012, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC120RE3DN" , 0x30012009, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC120VD2DN" , 0x30012022, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC120VD3DN" , 0x30012021, NUMICRO_BANKS_NUC100(64*1024)},
-	{"NUC120VE3DN" , 0x30012018, NUMICRO_BANKS_NUC100(128*1024)},
-	{"NUC130RC1DN" , 0x30013017, NUMICRO_BANKS_NUC100(32*1024)},
-
-	{"UNKNOWN"     , 0x00000000, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC100LC1DN",  0x30010008, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC100LD1DN",  0x30010005, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC100LD2DN",  0x30010004, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC100RC1DN",  0x30010017, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC100RD1DN",  0x30010014, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC100RD2DN",  0x30010013, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC100LD3DN",  0x30010003, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC100LE3DN",  0x30010000, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC100RD3DN",  0x30010012, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC100RE3DN",  0x30010009, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC100VD2DN",  0x30010022, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC100VD3DN",  0x30010021, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC100VE3DN",  0x30010018, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC120LC1DN",  0x30012008, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC120LD1DN",  0x30012005, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC120LD2DN",  0x30012004, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC120RC1DN",  0x30012017, NUMICRO_BANKS_NUC100(32*1024)},
+	{"NUC120RD1DN",  0x30012014, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC120RD2DN",  0x30012013, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC120LD3DN",  0x30012003, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC120LE3DN",  0x30012000, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC120RD3DN",  0x30012012, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC120RE3DN",  0x30012009, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC120VD2DN",  0x30012022, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC120VD3DN",  0x30012021, NUMICRO_BANKS_NUC100(64*1024)},
+	{"NUC120VE3DN",  0x30012018, NUMICRO_BANKS_NUC100(128*1024)},
+	{"NUC130RC1DN",  0x30013017, NUMICRO_BANKS_NUC100(32*1024)},
+
+	{"UNKNOWN",      0x00000000, NUMICRO_BANKS_NUC100(128*1024)},
 };
 
 /* Private bank information for NuMicro. */
@@ -1447,8 +1447,8 @@ static int numicro_protect_check(struct flash_bank *bank)
 		return retval;
 
 	/* Read CONFIG0,CONFIG1 */
-	numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG0, 0 , &config[0]);
-	numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG1, 0 , &config[1]);
+	numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG0, 0, &config[0]);
+	numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG1, 0, &config[1]);
 
 	LOG_DEBUG("CONFIG0: 0x%" PRIx32 ",CONFIG1: 0x%" PRIx32 "", config[0], config[1]);
 
diff --git a/src/jtag/drivers/opendous.c b/src/jtag/drivers/opendous.c
index bb223f4..5572c4a 100644
--- a/src/jtag/drivers/opendous.c
+++ b/src/jtag/drivers/opendous.c
@@ -596,7 +596,7 @@ void opendous_tap_append_step(int tms, int tdi)
 		if (!bits)
 			tms_buffer[tap_index] = 0;
 
-		tms_buffer[tap_index] |= (_tdi << bits)|(_tms << (bits + 1)) ;
+		tms_buffer[tap_index] |= (_tdi << bits)|(_tms << (bits + 1));
 		tap_length++;
 	} else
 		LOG_ERROR("opendous_tap_append_step, overflow");
diff --git a/src/jtag/hla/hla_layout.h b/src/jtag/hla/hla_layout.h
index 1d759e1..6805295 100644
--- a/src/jtag/hla/hla_layout.h
+++ b/src/jtag/hla/hla_layout.h
@@ -35,33 +35,33 @@ extern struct hl_layout_api_s icdi_usb_layout_api;
 /** */
 struct hl_layout_api_s {
 	/** */
-	int (*open) (struct hl_interface_param_s *param, void **handle);
+	int (*open)(struct hl_interface_param_s *param, void **handle);
 	/** */
-	int (*close) (void *handle);
+	int (*close)(void *handle);
 	/** */
-	int (*reset) (void *handle);
+	int (*reset)(void *handle);
 	/** */
-	int (*assert_srst) (void *handle, int srst);
+	int (*assert_srst)(void *handle, int srst);
 	/** */
-	int (*run) (void *handle);
+	int (*run)(void *handle);
 	/** */
-	int (*halt) (void *handle);
+	int (*halt)(void *handle);
 	/** */
-	int (*step) (void *handle);
+	int (*step)(void *handle);
 	/** */
-	int (*read_regs) (void *handle);
+	int (*read_regs)(void *handle);
 	/** */
-	int (*read_reg) (void *handle, int num, uint32_t *val);
+	int (*read_reg)(void *handle, int num, uint32_t *val);
 	/** */
-	int (*write_reg) (void *handle, int num, uint32_t val);
+	int (*write_reg)(void *handle, int num, uint32_t val);
 	/** */
-	int (*read_mem) (void *handle, uint32_t addr, uint32_t size,
+	int (*read_mem)(void *handle, uint32_t addr, uint32_t size,
 			uint32_t count, uint8_t *buffer);
 	/** */
-	int (*write_mem) (void *handle, uint32_t addr, uint32_t size,
+	int (*write_mem)(void *handle, uint32_t addr, uint32_t size,
 			uint32_t count, const uint8_t *buffer);
 	/** */
-	int (*write_debug_reg) (void *handle, uint32_t addr, uint32_t val);
+	int (*write_debug_reg)(void *handle, uint32_t addr, uint32_t val);
 	/**
 	 * Read the idcode of the target connected to the adapter
 	 *
@@ -72,11 +72,11 @@ struct hl_layout_api_s {
 	 * @param idcode Storage for the detected idcode
 	 * @returns ERROR_OK on success, or an error code on failure.
 	 */
-	int (*idcode) (void *handle, uint32_t *idcode);
+	int (*idcode)(void *handle, uint32_t *idcode);
 	/** */
-	int (*override_target) (const char *targetname);
+	int (*override_target)(const char *targetname);
 	/** */
-	int (*custom_command) (void *handle, const char *command);
+	int (*custom_command)(void *handle, const char *command);
 	/** */
 	int (*speed)(void *handle, int khz, bool query);
 	/**
@@ -107,7 +107,7 @@ struct hl_layout_api_s {
 	 */
 	int (*poll_trace)(void *handle, uint8_t *buf, size_t *size);
 	/** */
-	enum target_state (*state) (void *fd);
+	enum target_state (*state)(void *fd);
 };
 
 /** */
@@ -115,9 +115,9 @@ struct hl_layout {
 	/** */
 	char *name;
 	/** */
-	int (*open) (struct hl_interface_s *adapter);
+	int (*open)(struct hl_interface_s *adapter);
 	/** */
-	int (*close) (struct hl_interface_s *adapter);
+	int (*close)(struct hl_interface_s *adapter);
 	/** */
 	struct hl_layout_api_s *api;
 };
diff --git a/src/rtos/rtos_mqx_stackings.c b/src/rtos/rtos_mqx_stackings.c
index 1a8bdfc..404f017 100644
--- a/src/rtos/rtos_mqx_stackings.c
+++ b/src/rtos/rtos_mqx_stackings.c
@@ -64,7 +64,7 @@ static const struct stack_register_offset \
rtos_mqx_arm_v7m_stack_offsets[ARMV7M_  { ARMV7M_R10,  0x20, 32 }, /* r10  */
 	{ ARMV7M_R11,  0x24, 32 }, /* r11  */
 	{ ARMV7M_R12,  0x3C, 32 }, /* r12  */
-	{ ARMV7M_R13,   -2 , 32 }, /* sp   */
+	{ ARMV7M_R13,    -2, 32 }, /* sp   */
 	{ ARMV7M_R14,  0x28, 32 }, /* lr   */
 	{ ARMV7M_PC,   0x44, 32 }, /* pc   */
 	{ ARMV7M_xPSR, 0x48, 32 }, /* xPSR */
diff --git a/src/svf/svf.c b/src/svf/svf.c
index fd27417..81400c5 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -226,7 +226,7 @@ static int svf_getline(char **lineptr, size_t *n, FILE *stream);
 
 #define SVF_MAX_BUFFER_SIZE_TO_COMMIT   (1024 * 1024)
 static uint8_t *svf_tdi_buffer, *svf_tdo_buffer, *svf_mask_buffer;
-static int svf_buffer_index, svf_buffer_size ;
+static int svf_buffer_index, svf_buffer_size;
 static int svf_quiet;
 static int svf_nil;
 static int svf_ignore_error;
@@ -246,7 +246,7 @@ static int svf_last_printed_percentage = -1;
  * DEBUG, INFO, ERROR, USER
  */
 #define SVF_BUF_LOG(_lvl, _buf, _nbits, _desc)							\
-	svf_hexbuf_print(LOG_LVL_##_lvl ,  __FILE__, __LINE__, __func__, _buf, _nbits, \
_desc) +	svf_hexbuf_print(LOG_LVL_##_lvl,  __FILE__, __LINE__, __func__, _buf, \
_nbits, _desc)  
 static void svf_hexbuf_print(int dbg_lvl, const char *file, unsigned line,
 							 const char *function, const uint8_t *buf,
diff --git a/src/target/arc.c b/src/target/arc.c
index 823b9ed..3e080fa 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -218,7 +218,7 @@ static int arc_get_register(struct reg *reg)
 	reg->dirty = false;
 
 	LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
-			reg->number , desc->name, value);
+			reg->number, desc->name, value);
 
 
 	return ERROR_OK;
@@ -855,7 +855,7 @@ static int arc_save_context(struct target *target)
 			reg->valid = true;
 			reg->dirty = false;
 			LOG_DEBUG("Get aux register regnum=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
-				i , arc_reg->name, aux_values[aux_cnt]);
+				i, arc_reg->name, aux_values[aux_cnt]);
 		}
 	}
 
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 61f11f2..f9d82db 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1284,13 +1284,13 @@ static struct reg_data_type aarch64v[] = {
 };
 
 static struct reg_data_type_bitfield aarch64_cpsr_bits[] = {
-	{  0, 0 , REG_TYPE_UINT8 },
-	{  2, 3,  REG_TYPE_UINT8 },
-	{  4, 4 , REG_TYPE_UINT8 },
-	{  6, 6 , REG_TYPE_BOOL },
-	{  7, 7 , REG_TYPE_BOOL },
-	{  8, 8 , REG_TYPE_BOOL },
-	{  9, 9 , REG_TYPE_BOOL },
+	{  0,  0, REG_TYPE_UINT8 },
+	{  2,  3, REG_TYPE_UINT8 },
+	{  4,  4, REG_TYPE_UINT8 },
+	{  6,  6, REG_TYPE_BOOL },
+	{  7,  7, REG_TYPE_BOOL },
+	{  8,  8, REG_TYPE_BOOL },
+	{  9,  9, REG_TYPE_BOOL },
 	{ 20, 20, REG_TYPE_BOOL },
 	{ 21, 21, REG_TYPE_BOOL },
 	{ 28, 28, REG_TYPE_BOOL },
@@ -1303,16 +1303,16 @@ static struct reg_data_type_flags_field aarch64_cpsr_fields[] \
= {  { "SP",  aarch64_cpsr_bits + 0,  aarch64_cpsr_fields + 1 },
 	{ "EL",  aarch64_cpsr_bits + 1,  aarch64_cpsr_fields + 2 },
 	{ "nRW", aarch64_cpsr_bits + 2,  aarch64_cpsr_fields + 3 },
-	{ "F"  , aarch64_cpsr_bits + 3,  aarch64_cpsr_fields + 4 },
-	{ "I"  , aarch64_cpsr_bits + 4,  aarch64_cpsr_fields + 5 },
-	{ "A"  , aarch64_cpsr_bits + 5,  aarch64_cpsr_fields + 6 },
-	{ "D"  , aarch64_cpsr_bits + 6,  aarch64_cpsr_fields + 7 },
-	{ "IL" , aarch64_cpsr_bits + 7,  aarch64_cpsr_fields + 8 },
-	{ "SS" , aarch64_cpsr_bits + 8,  aarch64_cpsr_fields + 9 },
-	{ "V"  , aarch64_cpsr_bits + 9,  aarch64_cpsr_fields + 10 },
-	{ "C"  , aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
-	{ "Z"  , aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
-	{ "N"  , aarch64_cpsr_bits + 12, NULL }
+	{ "F",   aarch64_cpsr_bits + 3,  aarch64_cpsr_fields + 4 },
+	{ "I",   aarch64_cpsr_bits + 4,  aarch64_cpsr_fields + 5 },
+	{ "A",   aarch64_cpsr_bits + 5,  aarch64_cpsr_fields + 6 },
+	{ "D",   aarch64_cpsr_bits + 6,  aarch64_cpsr_fields + 7 },
+	{ "IL",  aarch64_cpsr_bits + 7,  aarch64_cpsr_fields + 8 },
+	{ "SS",  aarch64_cpsr_bits + 8,  aarch64_cpsr_fields + 9 },
+	{ "V",   aarch64_cpsr_bits + 9,  aarch64_cpsr_fields + 10 },
+	{ "C",   aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
+	{ "Z",   aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
+	{ "N",   aarch64_cpsr_bits + 12, NULL }
 };
 
 static struct reg_data_type_flags aarch64_cpsr_flags[] = {
diff --git a/src/target/dsp563xx.h b/src/target/dsp563xx.h
index 4bb5ace..18428b8 100644
--- a/src/target/dsp563xx.h
+++ b/src/target/dsp563xx.h
@@ -46,8 +46,8 @@ struct dsp563xx_common {
 	struct once_reg once_regs[DSP563XX_NUMONCEREGS];
 
 	/* register cache to processor synchronization */
-	int (*read_core_reg) (struct target *target, int num);
-	int (*write_core_reg) (struct target *target, int num);
+	int (*read_core_reg)(struct target *target, int num);
+	int (*write_core_reg)(struct target *target, int num);
 
 	struct hardware_breakpoint hardware_breakpoint[1];
 
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 5260032..3929a8c 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -226,7 +226,7 @@ static int mips32_write_core_reg(struct target *target, unsigned \
int num)  
 	reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
 	mips32->core_regs[num] = reg_value;
-	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
+	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
 	mips32->core_cache->reg_list[num].valid = true;
 	mips32->core_cache->reg_list[num].dirty = false;
 
diff --git a/src/target/mips64.c b/src/target/mips64.c
index 6a7c425..347cdfc 100644
--- a/src/target/mips64.c
+++ b/src/target/mips64.c
@@ -283,7 +283,7 @@ static int mips64_write_core_reg(struct target *target, int num)
 
 	reg_value = buf_get_u64(mips64->core_cache->reg_list[num].value, 0, 64);
 	mips64->core_regs[num] = reg_value;
-	LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num , reg_value);
+	LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
 	mips64->core_cache->reg_list[num].valid = 1;
 	mips64->core_cache->reg_list[num].dirty = 0;
 
diff --git a/src/target/nds32.c b/src/target/nds32.c
index f40ce53..0d1a23a8d 100644
--- a/src/target/nds32.c
+++ b/src/target/nds32.c
@@ -1711,8 +1711,8 @@ int nds32_cache_sync(struct target *target, target_addr_t \
address, uint32_t leng  /* (address + length - 1) / dcache_line_size */
 		end_line = (address + length - 1) >> (dcache->line_size + 2);
 
-		for (cur_address = address, cur_line = start_line ;
-				cur_line <= end_line ;
+		for (cur_address = address, cur_line = start_line;
+				cur_line <= end_line;
 				cur_address += dcache_line_size, cur_line++) {
 			/* D$ write back */
 			result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_VA_WB, cur_address);
@@ -1732,8 +1732,8 @@ int nds32_cache_sync(struct target *target, target_addr_t \
address, uint32_t leng  /* (address + length - 1) / icache_line_size */
 		end_line = (address + length - 1) >> (icache->line_size + 2);
 
-		for (cur_address = address, cur_line = start_line ;
-				cur_line <= end_line ;
+		for (cur_address = address, cur_line = start_line;
+				cur_line <= end_line;
 				cur_address += icache_line_size, cur_line++) {
 			/* Because PSW.IT is turned off under debug exception, address MUST
 			 * be physical address.  L1I_VA_INVALIDATE uses PSW.IT to decide
diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index 1e5db8c..5cd3bed 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -50,186 +50,186 @@ static int or1k_write_core_reg(struct target *target, int num);
 static struct or1k_core_reg *or1k_core_reg_list_arch_info;
 
 static const struct or1k_core_reg_init or1k_init_reg_list[] = {
-	{"r0"       , GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL},
-	{"r1"       , GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL},
-	{"r2"       , GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL},
-	{"r3"       , GROUP0 + 1027, "org.gnu.gdb.or1k.group0", NULL},
-	{"r4"       , GROUP0 + 1028, "org.gnu.gdb.or1k.group0", NULL},
-	{"r5"       , GROUP0 + 1029, "org.gnu.gdb.or1k.group0", NULL},
-	{"r6"       , GROUP0 + 1030, "org.gnu.gdb.or1k.group0", NULL},
-	{"r7"       , GROUP0 + 1031, "org.gnu.gdb.or1k.group0", NULL},
-	{"r8"       , GROUP0 + 1032, "org.gnu.gdb.or1k.group0", NULL},
-	{"r9"       , GROUP0 + 1033, "org.gnu.gdb.or1k.group0", NULL},
-	{"r10"      , GROUP0 + 1034, "org.gnu.gdb.or1k.group0", NULL},
-	{"r11"      , GROUP0 + 1035, "org.gnu.gdb.or1k.group0", NULL},
-	{"r12"      , GROUP0 + 1036, "org.gnu.gdb.or1k.group0", NULL},
-	{"r13"      , GROUP0 + 1037, "org.gnu.gdb.or1k.group0", NULL},
-	{"r14"      , GROUP0 + 1038, "org.gnu.gdb.or1k.group0", NULL},
-	{"r15"      , GROUP0 + 1039, "org.gnu.gdb.or1k.group0", NULL},
-	{"r16"      , GROUP0 + 1040, "org.gnu.gdb.or1k.group0", NULL},
-	{"r17"      , GROUP0 + 1041, "org.gnu.gdb.or1k.group0", NULL},
-	{"r18"      , GROUP0 + 1042, "org.gnu.gdb.or1k.group0", NULL},
-	{"r19"      , GROUP0 + 1043, "org.gnu.gdb.or1k.group0", NULL},
-	{"r20"      , GROUP0 + 1044, "org.gnu.gdb.or1k.group0", NULL},
-	{"r21"      , GROUP0 + 1045, "org.gnu.gdb.or1k.group0", NULL},
-	{"r22"      , GROUP0 + 1046, "org.gnu.gdb.or1k.group0", NULL},
-	{"r23"      , GROUP0 + 1047, "org.gnu.gdb.or1k.group0", NULL},
-	{"r24"      , GROUP0 + 1048, "org.gnu.gdb.or1k.group0", NULL},
-	{"r25"      , GROUP0 + 1049, "org.gnu.gdb.or1k.group0", NULL},
-	{"r26"      , GROUP0 + 1050, "org.gnu.gdb.or1k.group0", NULL},
-	{"r27"      , GROUP0 + 1051, "org.gnu.gdb.or1k.group0", NULL},
-	{"r28"      , GROUP0 + 1052, "org.gnu.gdb.or1k.group0", NULL},
-	{"r29"      , GROUP0 + 1053, "org.gnu.gdb.or1k.group0", NULL},
-	{"r30"      , GROUP0 + 1054, "org.gnu.gdb.or1k.group0", NULL},
-	{"r31"      , GROUP0 + 1055, "org.gnu.gdb.or1k.group0", NULL},
-	{"ppc"      , GROUP0 + 18,   "org.gnu.gdb.or1k.group0", NULL},
-	{"npc"      , GROUP0 + 16,   "org.gnu.gdb.or1k.group0", NULL},
-	{"sr"       , GROUP0 + 17,   "org.gnu.gdb.or1k.group0", NULL},
-	{"vr"       , GROUP0 + 0,    "org.gnu.gdb.or1k.group0", "system"},
-	{"upr"      , GROUP0 + 1,    "org.gnu.gdb.or1k.group0", "system"},
-	{"cpucfgr"  , GROUP0 + 2,    "org.gnu.gdb.or1k.group0", "system"},
-	{"dmmucfgr" , GROUP0 + 3,    "org.gnu.gdb.or1k.group0", "system"},
-	{"immucfgr" , GROUP0 + 4,    "org.gnu.gdb.or1k.group0", "system"},
-	{"dccfgr"   , GROUP0 + 5,    "org.gnu.gdb.or1k.group0", "system"},
-	{"iccfgr"   , GROUP0 + 6,    "org.gnu.gdb.or1k.group0", "system"},
-	{"dcfgr"    , GROUP0 + 7,    "org.gnu.gdb.or1k.group0", "system"},
-	{"pccfgr"   , GROUP0 + 8,    "org.gnu.gdb.or1k.group0", "system"},
-	{"fpcsr"    , GROUP0 + 20,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr0"    , GROUP0 + 32,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr1"    , GROUP0 + 33,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr2"    , GROUP0 + 34,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr3"    , GROUP0 + 35,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr4"    , GROUP0 + 36,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr5"    , GROUP0 + 37,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr6"    , GROUP0 + 38,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr7"    , GROUP0 + 39,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr8"    , GROUP0 + 40,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr9"    , GROUP0 + 41,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr10"   , GROUP0 + 42,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr11"   , GROUP0 + 43,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr12"   , GROUP0 + 44,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr13"   , GROUP0 + 45,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr14"   , GROUP0 + 46,   "org.gnu.gdb.or1k.group0", "system"},
-	{"epcr15"   , GROUP0 + 47,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear0"    , GROUP0 + 48,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear1"    , GROUP0 + 49,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear2"    , GROUP0 + 50,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear3"    , GROUP0 + 51,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear4"    , GROUP0 + 52,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear5"    , GROUP0 + 53,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear6"    , GROUP0 + 54,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear7"    , GROUP0 + 55,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear8"    , GROUP0 + 56,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear9"    , GROUP0 + 57,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear10"   , GROUP0 + 58,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear11"   , GROUP0 + 59,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear12"   , GROUP0 + 60,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear13"   , GROUP0 + 61,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear14"   , GROUP0 + 62,   "org.gnu.gdb.or1k.group0", "system"},
-	{"eear15"   , GROUP0 + 63,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr0"     , GROUP0 + 64,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr1"     , GROUP0 + 65,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr2"     , GROUP0 + 66,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr3"     , GROUP0 + 67,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr4"     , GROUP0 + 68,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr5"     , GROUP0 + 69,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr6"     , GROUP0 + 70,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr7"     , GROUP0 + 71,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr8"     , GROUP0 + 72,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr9"     , GROUP0 + 73,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr10"    , GROUP0 + 74,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr11"    , GROUP0 + 75,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr12"    , GROUP0 + 76,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr13"    , GROUP0 + 77,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr14"    , GROUP0 + 78,   "org.gnu.gdb.or1k.group0", "system"},
-	{"esr15"    , GROUP0 + 79,   "org.gnu.gdb.or1k.group0", "system"},
-
-	{"dmmuucr"  , GROUP1 + 0,    "org.gnu.gdb.or1k.group1", "dmmu"},
-	{"dmmuupr"  , GROUP1 + 1,    "org.gnu.gdb.or1k.group1", "dmmu"},
-	{"dtlbeir"  , GROUP1 + 2,    "org.gnu.gdb.or1k.group1", "dmmu"},
-	{"datbmr0"  , GROUP1 + 4,    "org.gnu.gdb.or1k.group1", "dmmu"},
-	{"datbmr1"  , GROUP1 + 5,    "org.gnu.gdb.or1k.group1", "dmmu"},
-	{"datbmr2"  , GROUP1 + 6,    "org.gnu.gdb.or1k.group1", "dmmu"},
-	{"datbmr3"  , GROUP1 + 7,    "org.gnu.gdb.or1k.group1", "dmmu"},
-	{"datbtr0"  , GROUP1 + 8,    "org.gnu.gdb.or1k.group1", "dmmu"},
-	{"datbtr1"  , GROUP1 + 9,    "org.gnu.gdb.or1k.group1", "dmmu"},
-	{"datbtr2"  , GROUP1 + 10,   "org.gnu.gdb.or1k.group1", "dmmu"},
-	{"datbtr3"  , GROUP1 + 11,   "org.gnu.gdb.or1k.group1", "dmmu"},
-
-	{"immucr"   , GROUP2 + 0,    "org.gnu.gdb.or1k.group2", "immu"},
-	{"immupr"   , GROUP2 + 1,    "org.gnu.gdb.or1k.group2", "immu"},
-	{"itlbeir"  , GROUP2 + 2,    "org.gnu.gdb.or1k.group2", "immu"},
-	{"iatbmr0"  , GROUP2 + 4,    "org.gnu.gdb.or1k.group2", "immu"},
-	{"iatbmr1"  , GROUP2 + 5,    "org.gnu.gdb.or1k.group2", "immu"},
-	{"iatbmr2"  , GROUP2 + 6,    "org.gnu.gdb.or1k.group2", "immu"},
-	{"iatbmr3"  , GROUP2 + 7,    "org.gnu.gdb.or1k.group2", "immu"},
-	{"iatbtr0"  , GROUP2 + 8,    "org.gnu.gdb.or1k.group2", "immu"},
-	{"iatbtr1"  , GROUP2 + 9,    "org.gnu.gdb.or1k.group2", "immu"},
-	{"iatbtr2"  , GROUP2 + 10,   "org.gnu.gdb.or1k.group2", "immu"},
-	{"iatbtr3"  , GROUP2 + 11,   "org.gnu.gdb.or1k.group2", "immu"},
-
-	{"dccr"     , GROUP3 + 0,    "org.gnu.gdb.or1k.group3", "dcache"},
-	{"dcbpr"    , GROUP3 + 1,    "org.gnu.gdb.or1k.group3", "dcache"},
-	{"dcbfr"    , GROUP3 + 2,    "org.gnu.gdb.or1k.group3", "dcache"},
-	{"dcbir"    , GROUP3 + 3,    "org.gnu.gdb.or1k.group3", "dcache"},
-	{"dcbwr"    , GROUP3 + 4,    "org.gnu.gdb.or1k.group3", "dcache"},
-	{"dcblr"    , GROUP3 + 5,    "org.gnu.gdb.or1k.group3", "dcache"},
-
-	{"iccr"     , GROUP4 + 0,    "org.gnu.gdb.or1k.group4", "icache"},
-	{"icbpr"    , GROUP4 + 1,    "org.gnu.gdb.or1k.group4", "icache"},
-	{"icbir"    , GROUP4 + 2,    "org.gnu.gdb.or1k.group4", "icache"},
-	{"icblr"    , GROUP4 + 3,    "org.gnu.gdb.or1k.group4", "icache"},
-
-	{"maclo"    , GROUP5 + 0,    "org.gnu.gdb.or1k.group5", "mac"},
-	{"machi"    , GROUP5 + 1,    "org.gnu.gdb.or1k.group5", "mac"},
-
-	{"dvr0"     , GROUP6 + 0,    "org.gnu.gdb.or1k.group6", "debug"},
-	{"dvr1"     , GROUP6 + 1,    "org.gnu.gdb.or1k.group6", "debug"},
-	{"dvr2"     , GROUP6 + 2,    "org.gnu.gdb.or1k.group6", "debug"},
-	{"dvr3"     , GROUP6 + 3,    "org.gnu.gdb.or1k.group6", "debug"},
-	{"dvr4"     , GROUP6 + 4,    "org.gnu.gdb.or1k.group6", "debug"},
-	{"dvr5"     , GROUP6 + 5,    "org.gnu.gdb.or1k.group6", "debug"},
-	{"dvr6"     , GROUP6 + 6,    "org.gnu.gdb.or1k.group6", "debug"},
-	{"dvr7"     , GROUP6 + 7,    "org.gnu.gdb.or1k.group6", "debug"},
-	{"dcr0"     , GROUP6 + 8,    "org.gnu.gdb.or1k.group6", "debug"},
-	{"dcr1"     , GROUP6 + 9,    "org.gnu.gdb.or1k.group6", "debug"},
-	{"dcr2"     , GROUP6 + 10,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"dcr3"     , GROUP6 + 11,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"dcr4"     , GROUP6 + 12,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"dcr5"     , GROUP6 + 13,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"dcr6"     , GROUP6 + 14,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"dcr7"     , GROUP6 + 15,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"dmr1"     , GROUP6 + 16,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"dmr2"     , GROUP6 + 17,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"dcwr0"    , GROUP6 + 18,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"dcwr1"    , GROUP6 + 19,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"dsr"      , GROUP6 + 20,   "org.gnu.gdb.or1k.group6", "debug"},
-	{"drr"      , GROUP6 + 21,   "org.gnu.gdb.or1k.group6", "debug"},
-
-	{"pccr0"    , GROUP7 + 0,    "org.gnu.gdb.or1k.group7", "perf"},
-	{"pccr1"    , GROUP7 + 1,    "org.gnu.gdb.or1k.group7", "perf"},
-	{"pccr2"    , GROUP7 + 2,    "org.gnu.gdb.or1k.group7", "perf"},
-	{"pccr3"    , GROUP7 + 3,    "org.gnu.gdb.or1k.group7", "perf"},
-	{"pccr4"    , GROUP7 + 4,    "org.gnu.gdb.or1k.group7", "perf"},
-	{"pccr5"    , GROUP7 + 5,    "org.gnu.gdb.or1k.group7", "perf"},
-	{"pccr6"    , GROUP7 + 6,    "org.gnu.gdb.or1k.group7", "perf"},
-	{"pccr7"    , GROUP7 + 7,    "org.gnu.gdb.or1k.group7", "perf"},
-	{"pcmr0"    , GROUP7 + 8,    "org.gnu.gdb.or1k.group7", "perf"},
-	{"pcmr1"    , GROUP7 + 9,    "org.gnu.gdb.or1k.group7", "perf"},
-	{"pcmr2"    , GROUP7 + 10,   "org.gnu.gdb.or1k.group7", "perf"},
-	{"pcmr3"    , GROUP7 + 11,   "org.gnu.gdb.or1k.group7", "perf"},
-	{"pcmr4"    , GROUP7 + 12,   "org.gnu.gdb.or1k.group7", "perf"},
-	{"pcmr5"    , GROUP7 + 13,   "org.gnu.gdb.or1k.group7", "perf"},
-	{"pcmr6"    , GROUP7 + 14,   "org.gnu.gdb.or1k.group7", "perf"},
-	{"pcmr7"    , GROUP7 + 15,   "org.gnu.gdb.or1k.group7", "perf"},
-
-	{"pmr"      , GROUP8 + 0,    "org.gnu.gdb.or1k.group8", "power"},
-
-	{"picmr"    , GROUP9 + 0,    "org.gnu.gdb.or1k.group9", "pic"},
-	{"picsr"    , GROUP9 + 2,    "org.gnu.gdb.or1k.group9", "pic"},
-
-	{"ttmr"     , GROUP10 + 0,   "org.gnu.gdb.or1k.group10", "timer"},
-	{"ttcr"     , GROUP10 + 1,   "org.gnu.gdb.or1k.group10", "timer"},
+	{"r0",        GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL},
+	{"r1",        GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL},
+	{"r2",        GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL},
+	{"r3",        GROUP0 + 1027, "org.gnu.gdb.or1k.group0", NULL},
+	{"r4",        GROUP0 + 1028, "org.gnu.gdb.or1k.group0", NULL},
+	{"r5",        GROUP0 + 1029, "org.gnu.gdb.or1k.group0", NULL},
+	{"r6",        GROUP0 + 1030, "org.gnu.gdb.or1k.group0", NULL},
+	{"r7",        GROUP0 + 1031, "org.gnu.gdb.or1k.group0", NULL},
+	{"r8",        GROUP0 + 1032, "org.gnu.gdb.or1k.group0", NULL},
+	{"r9",        GROUP0 + 1033, "org.gnu.gdb.or1k.group0", NULL},
+	{"r10",       GROUP0 + 1034, "org.gnu.gdb.or1k.group0", NULL},
+	{"r11",       GROUP0 + 1035, "org.gnu.gdb.or1k.group0", NULL},
+	{"r12",       GROUP0 + 1036, "org.gnu.gdb.or1k.group0", NULL},
+	{"r13",       GROUP0 + 1037, "org.gnu.gdb.or1k.group0", NULL},
+	{"r14",       GROUP0 + 1038, "org.gnu.gdb.or1k.group0", NULL},
+	{"r15",       GROUP0 + 1039, "org.gnu.gdb.or1k.group0", NULL},
+	{"r16",       GROUP0 + 1040, "org.gnu.gdb.or1k.group0", NULL},
+	{"r17",       GROUP0 + 1041, "org.gnu.gdb.or1k.group0", NULL},
+	{"r18",       GROUP0 + 1042, "org.gnu.gdb.or1k.group0", NULL},
+	{"r19",       GROUP0 + 1043, "org.gnu.gdb.or1k.group0", NULL},
+	{"r20",       GROUP0 + 1044, "org.gnu.gdb.or1k.group0", NULL},
+	{"r21",       GROUP0 + 1045, "org.gnu.gdb.or1k.group0", NULL},
+	{"r22",       GROUP0 + 1046, "org.gnu.gdb.or1k.group0", NULL},
+	{"r23",       GROUP0 + 1047, "org.gnu.gdb.or1k.group0", NULL},
+	{"r24",       GROUP0 + 1048, "org.gnu.gdb.or1k.group0", NULL},
+	{"r25",       GROUP0 + 1049, "org.gnu.gdb.or1k.group0", NULL},
+	{"r26",       GROUP0 + 1050, "org.gnu.gdb.or1k.group0", NULL},
+	{"r27",       GROUP0 + 1051, "org.gnu.gdb.or1k.group0", NULL},
+	{"r28",       GROUP0 + 1052, "org.gnu.gdb.or1k.group0", NULL},
+	{"r29",       GROUP0 + 1053, "org.gnu.gdb.or1k.group0", NULL},
+	{"r30",       GROUP0 + 1054, "org.gnu.gdb.or1k.group0", NULL},
+	{"r31",       GROUP0 + 1055, "org.gnu.gdb.or1k.group0", NULL},
+	{"ppc",       GROUP0 + 18,   "org.gnu.gdb.or1k.group0", NULL},
+	{"npc",       GROUP0 + 16,   "org.gnu.gdb.or1k.group0", NULL},
+	{"sr",        GROUP0 + 17,   "org.gnu.gdb.or1k.group0", NULL},
+	{"vr",        GROUP0 + 0,    "org.gnu.gdb.or1k.group0", "system"},
+	{"upr",       GROUP0 + 1,    "org.gnu.gdb.or1k.group0", "system"},
+	{"cpucfgr",   GROUP0 + 2,    "org.gnu.gdb.or1k.group0", "system"},
+	{"dmmucfgr",  GROUP0 + 3,    "org.gnu.gdb.or1k.group0", "system"},
+	{"immucfgr",  GROUP0 + 4,    "org.gnu.gdb.or1k.group0", "system"},
+	{"dccfgr",    GROUP0 + 5,    "org.gnu.gdb.or1k.group0", "system"},
+	{"iccfgr",    GROUP0 + 6,    "org.gnu.gdb.or1k.group0", "system"},
+	{"dcfgr",     GROUP0 + 7,    "org.gnu.gdb.or1k.group0", "system"},
+	{"pccfgr",    GROUP0 + 8,    "org.gnu.gdb.or1k.group0", "system"},
+	{"fpcsr",     GROUP0 + 20,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr0",     GROUP0 + 32,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr1",     GROUP0 + 33,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr2",     GROUP0 + 34,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr3",     GROUP0 + 35,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr4",     GROUP0 + 36,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr5",     GROUP0 + 37,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr6",     GROUP0 + 38,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr7",     GROUP0 + 39,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr8",     GROUP0 + 40,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr9",     GROUP0 + 41,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr10",    GROUP0 + 42,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr11",    GROUP0 + 43,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr12",    GROUP0 + 44,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr13",    GROUP0 + 45,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr14",    GROUP0 + 46,   "org.gnu.gdb.or1k.group0", "system"},
+	{"epcr15",    GROUP0 + 47,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear0",     GROUP0 + 48,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear1",     GROUP0 + 49,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear2",     GROUP0 + 50,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear3",     GROUP0 + 51,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear4",     GROUP0 + 52,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear5",     GROUP0 + 53,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear6",     GROUP0 + 54,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear7",     GROUP0 + 55,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear8",     GROUP0 + 56,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear9",     GROUP0 + 57,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear10",    GROUP0 + 58,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear11",    GROUP0 + 59,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear12",    GROUP0 + 60,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear13",    GROUP0 + 61,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear14",    GROUP0 + 62,   "org.gnu.gdb.or1k.group0", "system"},
+	{"eear15",    GROUP0 + 63,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr0",      GROUP0 + 64,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr1",      GROUP0 + 65,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr2",      GROUP0 + 66,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr3",      GROUP0 + 67,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr4",      GROUP0 + 68,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr5",      GROUP0 + 69,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr6",      GROUP0 + 70,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr7",      GROUP0 + 71,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr8",      GROUP0 + 72,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr9",      GROUP0 + 73,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr10",     GROUP0 + 74,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr11",     GROUP0 + 75,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr12",     GROUP0 + 76,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr13",     GROUP0 + 77,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr14",     GROUP0 + 78,   "org.gnu.gdb.or1k.group0", "system"},
+	{"esr15",     GROUP0 + 79,   "org.gnu.gdb.or1k.group0", "system"},
+
+	{"dmmuucr",   GROUP1 + 0,    "org.gnu.gdb.or1k.group1", "dmmu"},
+	{"dmmuupr",   GROUP1 + 1,    "org.gnu.gdb.or1k.group1", "dmmu"},
+	{"dtlbeir",   GROUP1 + 2,    "org.gnu.gdb.or1k.group1", "dmmu"},
+	{"datbmr0",   GROUP1 + 4,    "org.gnu.gdb.or1k.group1", "dmmu"},
+	{"datbmr1",   GROUP1 + 5,    "org.gnu.gdb.or1k.group1", "dmmu"},
+	{"datbmr2",   GROUP1 + 6,    "org.gnu.gdb.or1k.group1", "dmmu"},
+	{"datbmr3",   GROUP1 + 7,    "org.gnu.gdb.or1k.group1", "dmmu"},
+	{"datbtr0",   GROUP1 + 8,    "org.gnu.gdb.or1k.group1", "dmmu"},
+	{"datbtr1",   GROUP1 + 9,    "org.gnu.gdb.or1k.group1", "dmmu"},
+	{"datbtr2",   GROUP1 + 10,   "org.gnu.gdb.or1k.group1", "dmmu"},
+	{"datbtr3",   GROUP1 + 11,   "org.gnu.gdb.or1k.group1", "dmmu"},
+
+	{"immucr",    GROUP2 + 0,    "org.gnu.gdb.or1k.group2", "immu"},
+	{"immupr",    GROUP2 + 1,    "org.gnu.gdb.or1k.group2", "immu"},
+	{"itlbeir",   GROUP2 + 2,    "org.gnu.gdb.or1k.group2", "immu"},
+	{"iatbmr0",   GROUP2 + 4,    "org.gnu.gdb.or1k.group2", "immu"},
+	{"iatbmr1",   GROUP2 + 5,    "org.gnu.gdb.or1k.group2", "immu"},
+	{"iatbmr2",   GROUP2 + 6,    "org.gnu.gdb.or1k.group2", "immu"},
+	{"iatbmr3",   GROUP2 + 7,    "org.gnu.gdb.or1k.group2", "immu"},
+	{"iatbtr0",   GROUP2 + 8,    "org.gnu.gdb.or1k.group2", "immu"},
+	{"iatbtr1",   GROUP2 + 9,    "org.gnu.gdb.or1k.group2", "immu"},
+	{"iatbtr2",   GROUP2 + 10,   "org.gnu.gdb.or1k.group2", "immu"},
+	{"iatbtr3",   GROUP2 + 11,   "org.gnu.gdb.or1k.group2", "immu"},
+
+	{"dccr",      GROUP3 + 0,    "org.gnu.gdb.or1k.group3", "dcache"},
+	{"dcbpr",     GROUP3 + 1,    "org.gnu.gdb.or1k.group3", "dcache"},
+	{"dcbfr",     GROUP3 + 2,    "org.gnu.gdb.or1k.group3", "dcache"},
+	{"dcbir",     GROUP3 + 3,    "org.gnu.gdb.or1k.group3", "dcache"},
+	{"dcbwr",     GROUP3 + 4,    "org.gnu.gdb.or1k.group3", "dcache"},
+	{"dcblr",     GROUP3 + 5,    "org.gnu.gdb.or1k.group3", "dcache"},
+
+	{"iccr",      GROUP4 + 0,    "org.gnu.gdb.or1k.group4", "icache"},
+	{"icbpr",     GROUP4 + 1,    "org.gnu.gdb.or1k.group4", "icache"},
+	{"icbir",     GROUP4 + 2,    "org.gnu.gdb.or1k.group4", "icache"},
+	{"icblr",     GROUP4 + 3,    "org.gnu.gdb.or1k.group4", "icache"},
+
+	{"maclo",     GROUP5 + 0,    "org.gnu.gdb.or1k.group5", "mac"},
+	{"machi",     GROUP5 + 1,    "org.gnu.gdb.or1k.group5", "mac"},
+
+	{"dvr0",      GROUP6 + 0,    "org.gnu.gdb.or1k.group6", "debug"},
+	{"dvr1",      GROUP6 + 1,    "org.gnu.gdb.or1k.group6", "debug"},
+	{"dvr2",      GROUP6 + 2,    "org.gnu.gdb.or1k.group6", "debug"},
+	{"dvr3",      GROUP6 + 3,    "org.gnu.gdb.or1k.group6", "debug"},
+	{"dvr4",      GROUP6 + 4,    "org.gnu.gdb.or1k.group6", "debug"},
+	{"dvr5",      GROUP6 + 5,    "org.gnu.gdb.or1k.group6", "debug"},
+	{"dvr6",      GROUP6 + 6,    "org.gnu.gdb.or1k.group6", "debug"},
+	{"dvr7",      GROUP6 + 7,    "org.gnu.gdb.or1k.group6", "debug"},
+	{"dcr0",      GROUP6 + 8,    "org.gnu.gdb.or1k.group6", "debug"},
+	{"dcr1",      GROUP6 + 9,    "org.gnu.gdb.or1k.group6", "debug"},
+	{"dcr2",      GROUP6 + 10,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"dcr3",      GROUP6 + 11,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"dcr4",      GROUP6 + 12,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"dcr5",      GROUP6 + 13,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"dcr6",      GROUP6 + 14,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"dcr7",      GROUP6 + 15,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"dmr1",      GROUP6 + 16,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"dmr2",      GROUP6 + 17,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"dcwr0",     GROUP6 + 18,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"dcwr1",     GROUP6 + 19,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"dsr",       GROUP6 + 20,   "org.gnu.gdb.or1k.group6", "debug"},
+	{"drr",       GROUP6 + 21,   "org.gnu.gdb.or1k.group6", "debug"},
+
+	{"pccr0",     GROUP7 + 0,    "org.gnu.gdb.or1k.group7", "perf"},
+	{"pccr1",     GROUP7 + 1,    "org.gnu.gdb.or1k.group7", "perf"},
+	{"pccr2",     GROUP7 + 2,    "org.gnu.gdb.or1k.group7", "perf"},
+	{"pccr3",     GROUP7 + 3,    "org.gnu.gdb.or1k.group7", "perf"},
+	{"pccr4",     GROUP7 + 4,    "org.gnu.gdb.or1k.group7", "perf"},
+	{"pccr5",     GROUP7 + 5,    "org.gnu.gdb.or1k.group7", "perf"},
+	{"pccr6",     GROUP7 + 6,    "org.gnu.gdb.or1k.group7", "perf"},
+	{"pccr7",     GROUP7 + 7,    "org.gnu.gdb.or1k.group7", "perf"},
+	{"pcmr0",     GROUP7 + 8,    "org.gnu.gdb.or1k.group7", "perf"},
+	{"pcmr1",     GROUP7 + 9,    "org.gnu.gdb.or1k.group7", "perf"},
+	{"pcmr2",     GROUP7 + 10,   "org.gnu.gdb.or1k.group7", "perf"},
+	{"pcmr3",     GROUP7 + 11,   "org.gnu.gdb.or1k.group7", "perf"},
+	{"pcmr4",     GROUP7 + 12,   "org.gnu.gdb.or1k.group7", "perf"},
+	{"pcmr5",     GROUP7 + 13,   "org.gnu.gdb.or1k.group7", "perf"},
+	{"pcmr6",     GROUP7 + 14,   "org.gnu.gdb.or1k.group7", "perf"},
+	{"pcmr7",     GROUP7 + 15,   "org.gnu.gdb.or1k.group7", "perf"},
+
+	{"pmr",       GROUP8 + 0,    "org.gnu.gdb.or1k.group8", "power"},
+
+	{"picmr",     GROUP9 + 0,    "org.gnu.gdb.or1k.group9", "pic"},
+	{"picsr",     GROUP9 + 2,    "org.gnu.gdb.or1k.group9", "pic"},
+
+	{"ttmr",      GROUP10 + 0,   "org.gnu.gdb.or1k.group10", "timer"},
+	{"ttcr",      GROUP10 + 1,   "org.gnu.gdb.or1k.group10", "timer"},
 };
 
 static int or1k_add_reg(struct target *target, struct or1k_core_reg *new_reg)
@@ -423,7 +423,7 @@ static int or1k_read_core_reg(struct target *target, int num)
 	if ((num >= 0) && (num < OR1KNUMCOREREGS)) {
 		reg_value = or1k->core_regs[num];
 		buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
-		LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num , reg_value);
+		LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num, reg_value);
 		or1k->core_cache->reg_list[num].valid = true;
 		or1k->core_cache->reg_list[num].dirty = false;
 	} else {
@@ -435,7 +435,7 @@ static int or1k_read_core_reg(struct target *target, int num)
 			return retval;
 		}
 		buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
-		LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num , reg_value);
+		LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num, reg_value);
 	}
 
 	return ERROR_OK;
@@ -452,7 +452,7 @@ static int or1k_write_core_reg(struct target *target, int num)
 
 	uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32);
 	or1k->core_regs[num] = reg_value;
-	LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num , reg_value);
+	LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num, reg_value);
 	or1k->core_cache->reg_list[num].valid = true;
 	or1k->core_cache->reg_list[num].dirty = false;
 
diff --git a/src/target/stm8.c b/src/target/stm8.c
index 6b03bb5..630436d 100644
--- a/src/target/stm8.c
+++ b/src/target/stm8.c
@@ -1154,7 +1154,7 @@ static int stm8_read_core_reg(struct target *target, unsigned \
int num)  return ERROR_COMMAND_SYNTAX_ERROR;
 
 	reg_value = stm8->core_regs[num];
-	LOG_DEBUG("read core reg %i value 0x%" PRIx32 "", num , reg_value);
+	LOG_DEBUG("read core reg %i value 0x%" PRIx32 "", num, reg_value);
 	buf_set_u32(stm8->core_cache->reg_list[num].value, 0, 32, reg_value);
 	stm8->core_cache->reg_list[num].valid = true;
 	stm8->core_cache->reg_list[num].dirty = false;
@@ -1174,7 +1174,7 @@ static int stm8_write_core_reg(struct target *target, unsigned \
int num)  
 	reg_value = buf_get_u32(stm8->core_cache->reg_list[num].value, 0, 32);
 	stm8->core_regs[num] = reg_value;
-	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
+	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
 	stm8->core_cache->reg_list[num].valid = true;
 	stm8->core_cache->reg_list[num].dirty = false;
 
diff --git a/src/target/target.c b/src/target/target.c
index b0deadb..27c6e18 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -176,10 +176,10 @@ static const Jim_Nvp nvp_error_target[] = {
 	{ .value = ERROR_TARGET_TIMEOUT, .name = "err-timeout" },
 	{ .value = ERROR_TARGET_NOT_HALTED, .name = "err-not-halted" },
 	{ .value = ERROR_TARGET_FAILURE, .name = "err-failure" },
-	{ .value = ERROR_TARGET_UNALIGNED_ACCESS   , .name = "err-unaligned-access" },
-	{ .value = ERROR_TARGET_DATA_ABORT , .name = "err-data-abort" },
-	{ .value = ERROR_TARGET_RESOURCE_NOT_AVAILABLE , .name = \
                "err-resource-not-available" },
-	{ .value = ERROR_TARGET_TRANSLATION_FAULT  , .name = "err-translation-fault" },
+	{ .value = ERROR_TARGET_UNALIGNED_ACCESS, .name = "err-unaligned-access" },
+	{ .value = ERROR_TARGET_DATA_ABORT, .name = "err-data-abort" },
+	{ .value = ERROR_TARGET_RESOURCE_NOT_AVAILABLE, .name = \
"err-resource-not-available" }, +	{ .value = ERROR_TARGET_TRANSLATION_FAULT, .name = \
"err-translation-fault" },  { .value = ERROR_TARGET_NOT_RUNNING, .name = \
"err-not-running" },  { .value = ERROR_TARGET_NOT_EXAMINED, .name = \
"err-not-examined" },  { .value = -1, .name = NULL }
@@ -229,10 +229,10 @@ static const Jim_Nvp nvp_target_event[] = {
 	{ .value = TARGET_EVENT_GDB_DETACH, .name = "gdb-detach" },
 
 	{ .value = TARGET_EVENT_GDB_FLASH_WRITE_START, .name = "gdb-flash-write-start" },
-	{ .value = TARGET_EVENT_GDB_FLASH_WRITE_END  , .name = "gdb-flash-write-end"   },
+	{ .value = TARGET_EVENT_GDB_FLASH_WRITE_END,   .name = "gdb-flash-write-end"   },
 
 	{ .value = TARGET_EVENT_GDB_FLASH_ERASE_START, .name = "gdb-flash-erase-start" },
-	{ .value = TARGET_EVENT_GDB_FLASH_ERASE_END  , .name = "gdb-flash-erase-end" },
+	{ .value = TARGET_EVENT_GDB_FLASH_ERASE_END,   .name = "gdb-flash-erase-end" },
 
 	{ .value = TARGET_EVENT_TRACE_CONFIG, .name = "trace-config" },
 
@@ -249,15 +249,15 @@ static const Jim_Nvp nvp_target_state[] = {
 };
 
 static const Jim_Nvp nvp_target_debug_reason[] = {
-	{ .name = "debug-request"            , .value = DBG_REASON_DBGRQ },
-	{ .name = "breakpoint"               , .value = DBG_REASON_BREAKPOINT },
-	{ .name = "watchpoint"               , .value = DBG_REASON_WATCHPOINT },
+	{ .name = "debug-request",             .value = DBG_REASON_DBGRQ },
+	{ .name = "breakpoint",                .value = DBG_REASON_BREAKPOINT },
+	{ .name = "watchpoint",                .value = DBG_REASON_WATCHPOINT },
 	{ .name = "watchpoint-and-breakpoint", .value = DBG_REASON_WPTANDBKPT },
-	{ .name = "single-step"              , .value = DBG_REASON_SINGLESTEP },
-	{ .name = "target-not-halted"        , .value = DBG_REASON_NOTHALTED  },
-	{ .name = "program-exit"             , .value = DBG_REASON_EXIT },
-	{ .name = "exception-catch"          , .value = DBG_REASON_EXC_CATCH },
-	{ .name = "undefined"                , .value = DBG_REASON_UNDEFINED },
+	{ .name = "single-step",               .value = DBG_REASON_SINGLESTEP },
+	{ .name = "target-not-halted",         .value = DBG_REASON_NOTHALTED  },
+	{ .name = "program-exit",              .value = DBG_REASON_EXIT },
+	{ .name = "exception-catch",           .value = DBG_REASON_EXC_CATCH },
+	{ .name = "undefined",                 .value = DBG_REASON_UNDEFINED },
 	{ .name = NULL, .value = -1 },
 };
 
@@ -271,10 +271,10 @@ static const Jim_Nvp nvp_target_endian[] = {
 
 static const Jim_Nvp nvp_reset_modes[] = {
 	{ .name = "unknown", .value = RESET_UNKNOWN },
-	{ .name = "run"    , .value = RESET_RUN },
-	{ .name = "halt"   , .value = RESET_HALT },
-	{ .name = "init"   , .value = RESET_INIT },
-	{ .name = NULL     , .value = -1 },
+	{ .name = "run",     .value = RESET_RUN },
+	{ .name = "halt",    .value = RESET_HALT },
+	{ .name = "init",    .value = RESET_INIT },
+	{ .name = NULL,      .value = -1 },
 };
 
 const char *debug_reason_name(struct target *t)
@@ -2892,7 +2892,7 @@ COMMAND_HANDLER(handle_reg_command)
 				} else {
 					command_print(CMD, "(%i) %s (/%" PRIu32 ")",
 							  count, reg->name,
-							  reg->size) ;
+							  reg->size);
 				}
 			}
 			cache = cache->next;
@@ -4639,7 +4639,7 @@ static Jim_Nvp nvp_config_opts[] = {
 	{ .name = "-work-area-phys",   .value = TCFG_WORK_AREA_PHYS },
 	{ .name = "-work-area-size",   .value = TCFG_WORK_AREA_SIZE },
 	{ .name = "-work-area-backup", .value = TCFG_WORK_AREA_BACKUP },
-	{ .name = "-endian" ,          .value = TCFG_ENDIAN },
+	{ .name = "-endian",           .value = TCFG_ENDIAN },
 	{ .name = "-coreid",           .value = TCFG_COREID },
 	{ .name = "-chain-position",   .value = TCFG_CHAIN_POSITION },
 	{ .name = "-dbgbase",          .value = TCFG_DBGBASE },

-- 


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