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List: openocd-development
Subject: [OpenOCD-devel] [PATCH]: 0c009f8 tcl: replace the deprecated commands with "adapter ..."
From: gerrit () openocd ! org (gerrit)
Date: 2019-08-23 14:09:35
Message-ID: 20190823140935.BBF952522575 () mail ! openocd ! org
[Download RAW message or body]
This is an automated email from Gerrit.
Antonio Borneo (borneo.antonio@gmail.com) just uploaded a new patch set to Gerrit, \
which you can find at http://openocd.zylin.com/5284
-- gerrit
commit 0c009f8e71c31400b6ac3ca32ab22f6749113412
Author: Antonio Borneo <borneo.antonio@gmail.com>
Date: Fri Aug 23 15:51:00 2019 +0200
tcl: replace the deprecated commands with "adapter ..."
Avoid annoying "deprecated" messages while running the scripts
distributed with OpenOCD code.
Change automatically created with commands
sed -i 's/adapter_khz/adapter speed/g' $(find tcl/ -type f)
sed -i 's/adapter_nsrst_delay/adapter srst delay/g' $(find tcl/ -type f)
sed -i 's/adapter_nsrst_assert_width/adapter srst pulse_width/g' $(find tcl/ \
-type f)
Minor indentation issue fixed manually in
tcl/board/at91sam9g20-ek.cfg
tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
Change-Id: I425fd56c0c88cd6b06124621306eeb89166dfe71
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
diff --git a/tcl/board/actux3.cfg b/tcl/board/actux3.cfg
index 5435ff8..0de4cb4 100644
--- a/tcl/board/actux3.cfg
+++ b/tcl/board/actux3.cfg
@@ -4,7 +4,7 @@
reset_config trst_and_srst separate
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
source [find target/ixp42x.cfg]
diff --git a/tcl/board/adsp-sc584-ezbrd.cfg b/tcl/board/adsp-sc584-ezbrd.cfg
index 1054a94..439fe92 100644
--- a/tcl/board/adsp-sc584-ezbrd.cfg
+++ b/tcl/board/adsp-sc584-ezbrd.cfg
@@ -25,7 +25,7 @@ source [find interface/jlink.cfg]
transport select swd
# chosen speed is 'safe' choice, but your adapter may be capable of more
-adapter_khz 400
+adapter speed 400
source [find target/adsp-sc58x.cfg]
diff --git a/tcl/board/altera_sockit.cfg b/tcl/board/altera_sockit.cfg
index 1466bd4..3fd01be 100644
--- a/tcl/board/altera_sockit.cfg
+++ b/tcl/board/altera_sockit.cfg
@@ -15,5 +15,5 @@ source [find target/altera_fpgasoc.cfg]
#usb_blaster_vid_pid 0x6810 0x09fb
#usb_blaster_device_desc "USB-Blaster II"
-adapter_khz 100
+adapter speed 100
diff --git a/tcl/board/arm_musca_a.cfg b/tcl/board/arm_musca_a.cfg
index fa7cf5e..25f8ce6 100644
--- a/tcl/board/arm_musca_a.cfg
+++ b/tcl/board/arm_musca_a.cfg
@@ -15,7 +15,7 @@
source [find target/swj-dp.tcl]
# set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
global _CHIPNAME
if { [info exists CHIPNAME] } {
diff --git a/tcl/board/arty_s7.cfg b/tcl/board/arty_s7.cfg
index ca7d3f1..5ab4083 100644
--- a/tcl/board/arty_s7.cfg
+++ b/tcl/board/arty_s7.cfg
@@ -10,7 +10,7 @@ source [find interface/ftdi/digilent-hs1.cfg]
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
-adapter_khz 25000
+adapter speed 25000
# Usage:
#
diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg
index 9bc02e8..a0e393f 100644
--- a/tcl/board/at91cap7a-stk-sdram.cfg
+++ b/tcl/board/at91cap7a-stk-sdram.cfg
@@ -28,7 +28,7 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN \
-chain-position $_TARGETNAM
$_TARGETNAME configure -event reset-start {
# start off real slow when we're running off internal RC oscillator
- adapter_khz 32
+ adapter speed 32
}
proc peek32 {address} {
@@ -78,7 +78,7 @@ $_TARGETNAME configure -event reset-init {
echo "Master clock ok."
# Now that we're up and running, crank up speed!
- global post_reset_khz ; adapter_khz $post_reset_khz
+ global post_reset_khz ; adapter speed $post_reset_khz
echo "Configuring the SDRAM controller..."
diff --git a/tcl/board/at91eb40a.cfg b/tcl/board/at91eb40a.cfg
index d8a82a5..d314e18 100644
--- a/tcl/board/at91eb40a.cfg
+++ b/tcl/board/at91eb40a.cfg
@@ -64,4 +64,4 @@ $_TARGETNAME configure -event reset-init {
}
# This target is pretty snappy...
-adapter_khz 16000
+adapter speed 16000
diff --git a/tcl/board/at91rm9200-dk.cfg b/tcl/board/at91rm9200-dk.cfg
index f484fde..b8ec00e 100644
--- a/tcl/board/at91rm9200-dk.cfg
+++ b/tcl/board/at91rm9200-dk.cfg
@@ -19,7 +19,7 @@ flash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME
proc at91rm9200_dk_init { } {
# Try to run at 1khz... Yea, that slow!
# Chip is really running @ 32khz
- adapter_khz 8
+ adapter speed 8
mww 0xfffffc64 0xffffffff
## disable all clocks but system clock
@@ -45,7 +45,7 @@ proc at91rm9200_dk_init { } {
#========================================
# CPU now runs at 180mhz
# SYS runs at 60mhz.
- adapter_khz 40000
+ adapter speed 40000
#========================================
diff --git a/tcl/board/at91rm9200-ek.cfg b/tcl/board/at91rm9200-ek.cfg
index a3f253a..958bc9d 100644
--- a/tcl/board/at91rm9200-ek.cfg
+++ b/tcl/board/at91rm9200-ek.cfg
@@ -19,12 +19,12 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
# The chip may run @ 32khz, so set a really low JTAG speed
-adapter_khz 8
+adapter speed 8
proc at91rm9200_ek_init { } {
# Try to run at 1khz... Yea, that slow!
# Chip is really running @ 32khz
- adapter_khz 8
+ adapter speed 8
mww 0xfffffc64 0xffffffff
## disable all clocks but system clock
@@ -61,7 +61,7 @@ proc at91rm9200_ek_init { } {
#========================================
# CPU now runs at 180mhz
# SYS runs at 60mhz.
- adapter_khz 40000
+ adapter speed 40000
#========================================
## Init SDRAM
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 741d601..773c889 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -19,7 +19,7 @@ set _FLASHTYPE nandflash_cs3
reset_config srst_only
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
# If you don't want to execute built-in boot rom code (and there are good reasons at \
times not to do that) in the @@ -54,7 +54,7 @@ proc at91sam9g20_reset_start { } {
# jtag speed without causing GDB keep alive problem.
arm7_9 fast_memory_access disable
- adapter_khz 2 ;# Slow-speed oscillator enabled at reset, so run \
jtag speed slow. + adapter speed 2 ;# Slow-speed oscillator enabled \
at reset, so run jtag speed slow. halt ;# Make sure \
processor is halted, or error will result in following steps. wait_halt 10000
mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset.
@@ -103,7 +103,7 @@ proc at91sam9g20_reset_init { } {
# Switch over to adaptive clocking.
- adapter_khz 0
+ adapter speed 0
# Enable faster DCC downloads and memory accesses.
diff --git a/tcl/board/atmel_sam3n_ek.cfg b/tcl/board/atmel_sam3n_ek.cfg
index 2ae73eb..e43008f 100644
--- a/tcl/board/atmel_sam3n_ek.cfg
+++ b/tcl/board/atmel_sam3n_ek.cfg
@@ -7,6 +7,6 @@ reset_config srst_only
set CHIPNAME at91sam3n4c
-adapter_khz 32
+adapter speed 32
source [find target/at91sam3nXX.cfg]
diff --git a/tcl/board/avnet_ultrazed-eg.cfg b/tcl/board/avnet_ultrazed-eg.cfg
index 9879bfc..3e4a11a 100644
--- a/tcl/board/avnet_ultrazed-eg.cfg
+++ b/tcl/board/avnet_ultrazed-eg.cfg
@@ -9,7 +9,7 @@ transport select jtag
reset_config none
# slow default clock
-adapter_khz 1000
+adapter speed 1000
set CHIPNAME uscale
diff --git a/tcl/board/bcm28155_ap.cfg b/tcl/board/bcm28155_ap.cfg
index fb729e1..770ff9c 100644
--- a/tcl/board/bcm28155_ap.cfg
+++ b/tcl/board/bcm28155_ap.cfg
@@ -1,6 +1,6 @@
# BCM28155_AP
-adapter_khz 20000
+adapter speed 20000
set CHIPNAME bcm28155
source [find target/bcm281xx.cfg]
diff --git a/tcl/board/colibri.cfg b/tcl/board/colibri.cfg
index 7c1f1cb..fe9a3d5 100644
--- a/tcl/board/colibri.cfg
+++ b/tcl/board/colibri.cfg
@@ -1,7 +1,7 @@
# Toradex Colibri PXA270
source [find target/pxa270.cfg]
reset_config trst_and_srst srst_push_pull
-adapter_nsrst_assert_width 40
+adapter srst pulse_width 40
# CS0 -- one bank of CFI flash, 32 MBytes
# the bank is 32-bits wide, two 16-bit chips in parallel
diff --git a/tcl/board/crossbow_tech_imote2.cfg b/tcl/board/crossbow_tech_imote2.cfg
index 002b537..277c353 100644
--- a/tcl/board/crossbow_tech_imote2.cfg
+++ b/tcl/board/crossbow_tech_imote2.cfg
@@ -4,7 +4,7 @@ set CHIPNAME imote2
source [find target/pxa270.cfg]
# longer-than-normal reset delay
-adapter_nsrst_delay 800
+adapter srst delay 800
reset_config trst_and_srst separate
diff --git a/tcl/board/csb337.cfg b/tcl/board/csb337.cfg
index 5e225f5..a9d0139 100644
--- a/tcl/board/csb337.cfg
+++ b/tcl/board/csb337.cfg
@@ -19,7 +19,7 @@ if { [info exists ETM_DRIVER] } {
proc csb337_clk_init { } {
# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
- adapter_khz 8
+ adapter speed 8
# CKGR_MOR: start main oscillator (3.6864 MHz)
mww 0xfffffc20 0xff01
@@ -37,7 +37,7 @@ proc csb337_clk_init { } {
sleep 20
# CPU is in Normal Mode ... allows faster JTAG clock speed
- adapter_khz 40000
+ adapter speed 40000
}
proc csb337_nor_init { } {
diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 4d6f0e4..35e397f 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -3,7 +3,7 @@ source [find target/imx35.cfg]
# Determined by trial and error
reset_config trst_and_srst combined
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
$_TARGETNAME configure -event gdb-attach { reset init }
diff --git a/tcl/board/digi_connectcore_wi-9c.cfg \
b/tcl/board/digi_connectcore_wi-9c.cfg index 8a8d4c3..43ad1c9 100644
--- a/tcl/board/digi_connectcore_wi-9c.cfg
+++ b/tcl/board/digi_connectcore_wi-9c.cfg
@@ -36,7 +36,7 @@ if { [info exists CPUTAPID] } {
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id \
$_CPUTAPID
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 0
diff --git a/tcl/board/digilent_analog_discovery.cfg \
b/tcl/board/digilent_analog_discovery.cfg index 65eb660..954e540 100644
--- a/tcl/board/digilent_analog_discovery.cfg
+++ b/tcl/board/digilent_analog_discovery.cfg
@@ -13,6 +13,6 @@ ftdi_vid_pid 0x0403 0x6014
ftdi_layout_init 0x8008 0x800b
-adapter_khz 25000
+adapter speed 25000
source [find cpld/xilinx-xc6s.cfg]
diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg
index 8f268c4..ed34c4b 100644
--- a/tcl/board/dm365evm.cfg
+++ b/tcl/board/dm365evm.cfg
@@ -103,7 +103,7 @@ proc dm365evm_init {} {
echo "Initialize DM365 EVM board"
# CLKIN = 24 MHz ... can't talk quickly to ARM yet
- adapter_khz 1500
+ adapter speed 1500
# FIXME -- PLL init
diff --git a/tcl/board/dp_busblaster_v3.cfg b/tcl/board/dp_busblaster_v3.cfg
index f21197b..a9974d9 100644
--- a/tcl/board/dp_busblaster_v3.cfg
+++ b/tcl/board/dp_busblaster_v3.cfg
@@ -4,7 +4,7 @@
# http://dangerousprototypes.com/docs/Bus_Blaster
#
# To reprogram the on-board CPLD do:
-# openocd -f board/dp_busblaster_v3.cfg -c "adapter_khz 1000; init; svf \
<path_to_svf>; shutdown" +# openocd -f board/dp_busblaster_v3.cfg -c "adapter speed \
1000; init; svf <path_to_svf>; shutdown" #
source [find interface/ftdi/dp_busblaster.cfg]
diff --git a/tcl/board/efm32.cfg b/tcl/board/efm32.cfg
index d2bc9a6..adbdda7 100644
--- a/tcl/board/efm32.cfg
+++ b/tcl/board/efm32.cfg
@@ -5,7 +5,7 @@
source [find interface/jlink.cfg]
transport select swd
-adapter_khz 1000
+adapter speed 1000
set CHIPNAME efm32
source [find target/efm32.cfg]
diff --git a/tcl/board/ek-lm3s1968.cfg b/tcl/board/ek-lm3s1968.cfg
index 8d990b1..bbb04ba 100644
--- a/tcl/board/ek-lm3s1968.cfg
+++ b/tcl/board/ek-lm3s1968.cfg
@@ -5,7 +5,7 @@
#
# NOTE: to use J-Link instead of the on-board interface,
-# you may also need to reduce adapter_khz to be about 1200.
+# you may also need to reduce adapter speed to be about 1200.
# source [find interface/jlink.cfg]
# include the FT2232 interface config for on-board JTAG interface
diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg \
b/tcl/board/embedded-artists_lpc2478-32.cfg index b036cd6..6c3aec6 100644
--- a/tcl/board/embedded-artists_lpc2478-32.cfg
+++ b/tcl/board/embedded-artists_lpc2478-32.cfg
@@ -15,7 +15,7 @@ proc read_register {register} {
proc init_board {} {
# Delays on reset lines
- adapter_nsrst_delay 500
+ adapter srst delay 500
jtag_ntrst_delay 1
# Adaptive JTAG clocking through RTCK.
diff --git a/tcl/board/emcraft_imx8m-som-bsb.cfg \
b/tcl/board/emcraft_imx8m-som-bsb.cfg index 5571d0e..248c0d4000 100644
--- a/tcl/board/emcraft_imx8m-som-bsb.cfg
+++ b/tcl/board/emcraft_imx8m-som-bsb.cfg
@@ -6,13 +6,13 @@
transport select jtag
# set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
# SRST and TRST are wired up
reset_config trst_and_srst
# delay after SRST goes inactive
-adapter_nsrst_delay 70
+adapter srst delay 70
# board has an i.MX8MQ with 4 Cortex-A53 cores
set CHIPNAME imx8mq
diff --git a/tcl/board/ethernut3.cfg b/tcl/board/ethernut3.cfg
index ad45527..72fc5ad 100644
--- a/tcl/board/ethernut3.cfg
+++ b/tcl/board/ethernut3.cfg
@@ -20,13 +20,13 @@ flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
# Micrel MIC2775-29YM5 Supervisor
# Reset output will remain active for 280ms (maximum)
#
-adapter_nsrst_delay 300
+adapter srst delay 300
jtag_ntrst_delay 300
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
-adapter_khz 16000
+adapter speed 16000
# Target events
diff --git a/tcl/board/fsl_imx6q_sabresd.cfg b/tcl/board/fsl_imx6q_sabresd.cfg
index e1f0892..cf34cd1 100644
--- a/tcl/board/fsl_imx6q_sabresd.cfg
+++ b/tcl/board/fsl_imx6q_sabresd.cfg
@@ -13,7 +13,7 @@ transport select jtag
# iMX6Q POR gates JTAG and the chip is completely incommunicado
# over JTAG for at least 10ms after nSRST is deasserted
-adapter_nsrst_delay 11
+adapter srst delay 11
# Source generic iMX6Q target configuration
set CHIPNAME imx6q
@@ -144,4 +144,4 @@ $_TARGETNAME.0 configure -event reset-assert { }
# hook the init function into the reset-init event
$_TARGETNAME.0 configure -event reset-init { imx6q_sabresd_init }
# set a slow default JTAG clock, can be overridden later
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/board/glyn_tonga2.cfg b/tcl/board/glyn_tonga2.cfg
index 17ed3cf..31aa9ff 100644
--- a/tcl/board/glyn_tonga2.cfg
+++ b/tcl/board/glyn_tonga2.cfg
@@ -19,12 +19,12 @@ source [find target/tmpa900.cfg]
# Initial JTAG speed should not exceed 1/6 of the initial CPU clock
# frequency (24MHz). Be conservative and use 1/8 of the frequency.
# (24MHz / 8 = 3MHz)
-adapter_khz 3000
+adapter speed 3000
$_TARGETNAME configure -event reset-start {
# Upon reset, set the JTAG frequency to 3MHz again, see above.
echo "Setting JTAG speed to 3MHz until clocks are initialized."
- adapter_khz 3000
+ adapter speed 3000
# Halt the CPU.
halt
@@ -41,7 +41,7 @@ $_TARGETNAME configure -event reset-init {
# Tests showed that 15MHz works OK, higher speeds can cause problems,
# though. Not sure if this is a CPU issue or JTAG adapter issue.
echo "Increasing JTAG speed to 15MHz."
- adapter_khz 15000
+ adapter speed 15000
# Enable faster memory access.
arm7_9 fast_memory_access enable
diff --git a/tcl/board/hilscher_nxdb500sys.cfg b/tcl/board/hilscher_nxdb500sys.cfg
index 77073e7..d71c445 100644
--- a/tcl/board/hilscher_nxdb500sys.cfg
+++ b/tcl/board/hilscher_nxdb500sys.cfg
@@ -5,7 +5,7 @@
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size \
0x4000 -work-area-backup 1
diff --git a/tcl/board/hilscher_nxeb500hmi.cfg b/tcl/board/hilscher_nxeb500hmi.cfg
index 6439156..aa3d587 100644
--- a/tcl/board/hilscher_nxeb500hmi.cfg
+++ b/tcl/board/hilscher_nxeb500hmi.cfg
@@ -5,7 +5,7 @@
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size \
0x4000 -work-area-backup 1
diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg
index 4ef2f3b..7ff9916 100644
--- a/tcl/board/hilscher_nxhx10.cfg
+++ b/tcl/board/hilscher_nxhx10.cfg
@@ -9,7 +9,7 @@ source [find target/hilscher_netx10.cfg]
# problems try to line below
# reset_config trst_and_srst srst_pulls_trst
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 \
-work-area-size 0x4000 -work-area-backup 1
diff --git a/tcl/board/hilscher_nxhx50.cfg b/tcl/board/hilscher_nxhx50.cfg
index eebb165..0867f2e 100644
--- a/tcl/board/hilscher_nxhx50.cfg
+++ b/tcl/board/hilscher_nxhx50.cfg
@@ -5,7 +5,7 @@
source [find target/hilscher_netx50.cfg]
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 \
-work-area-size 0x4000 -work-area-backup 1
diff --git a/tcl/board/hilscher_nxhx500.cfg b/tcl/board/hilscher_nxhx500.cfg
index dd3a951..2ba030e 100644
--- a/tcl/board/hilscher_nxhx500.cfg
+++ b/tcl/board/hilscher_nxhx500.cfg
@@ -5,7 +5,7 @@
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size \
0x4000 -work-area-backup 1
diff --git a/tcl/board/hilscher_nxsb100.cfg b/tcl/board/hilscher_nxsb100.cfg
index efb091b..807e292 100644
--- a/tcl/board/hilscher_nxsb100.cfg
+++ b/tcl/board/hilscher_nxsb100.cfg
@@ -5,7 +5,7 @@
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size \
0x4000 -work-area-backup 1
diff --git a/tcl/board/hitex_lpc1768stick.cfg b/tcl/board/hitex_lpc1768stick.cfg
index 161e965..8c11936 100644
--- a/tcl/board/hitex_lpc1768stick.cfg
+++ b/tcl/board/hitex_lpc1768stick.cfg
@@ -11,5 +11,5 @@ source [find target/lpc17xx.cfg]
# startup @ 500kHz
-adapter_khz 500
+adapter speed 500
diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg
index d251537..f517798 100644
--- a/tcl/board/hitex_lpc2929.cfg
+++ b/tcl/board/hitex_lpc2929.cfg
@@ -2,12 +2,12 @@
# http://www.hitex.com/
# Delays on reset lines
-adapter_nsrst_delay 50
+adapter srst delay 50
jtag_ntrst_delay 1
# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
# Adaptive clocking through RTCK is not supported.
-adapter_khz 2000
+adapter speed 2000
# Target device: LPC29xx with ETB
# The following variables are used by the LPC2900 script:
@@ -24,7 +24,7 @@ $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size \
0x10000 -work- # Event handlers
$_TARGETNAME configure -event reset-start {
# Back to the slow JTAG clock
- adapter_khz 2000
+ adapter speed 2000
}
# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
@@ -46,7 +46,7 @@ $_TARGETNAME configure -event reset-init {
mww 0xFFFF8070 0x02000000 ;# SYS_CLK_CONF: PLL
# Increase JTAG speed
- adapter_khz 6000
+ adapter speed 6000
# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
mww 0xE0001138 0x0000001F ;# P1.14 = D0
diff --git a/tcl/board/hitex_stm32-performancestick.cfg \
b/tcl/board/hitex_stm32-performancestick.cfg index 82fb169..738178a 100644
--- a/tcl/board/hitex_stm32-performancestick.cfg
+++ b/tcl/board/hitex_stm32-performancestick.cfg
@@ -12,5 +12,5 @@ source [find target/stm32f1x.cfg]
jtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041
# for some reason this board like to startup @ 500kHz
-adapter_khz 500
+adapter speed 500
diff --git a/tcl/board/hitex_str9-comstick.cfg b/tcl/board/hitex_str9-comstick.cfg
index be15331..3b92252 100644
--- a/tcl/board/hitex_str9-comstick.cfg
+++ b/tcl/board/hitex_str9-comstick.cfg
@@ -5,9 +5,9 @@
source [find interface/ftdi/hitex_str9-comstick.cfg]
# set jtag speed
-adapter_khz 3000
+adapter speed 3000
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg
index aa6a148..2345ef1 100644
--- a/tcl/board/icnova_imx53_sodimm.cfg
+++ b/tcl/board/icnova_imx53_sodimm.cfg
@@ -15,7 +15,7 @@ echo "i.MX53 SO-Dimm board lodaded."
# Set reset type
#reset_config srst_only
-adapter_khz 3000
+adapter speed 3000
# Slow speed to be sure it will work
jtag_rclk 1000
@@ -58,7 +58,7 @@ proc sodimm_init { } {
arm core_state arm
jtag_rclk 3000
-# adapter_khz 3000
+# adapter speed 3000
}
diff --git a/tcl/board/icnova_sam9g45_sodimm.cfg \
b/tcl/board/icnova_sam9g45_sodimm.cfg index 84dab38..bf70cca 100644
--- a/tcl/board/icnova_sam9g45_sodimm.cfg
+++ b/tcl/board/icnova_sam9g45_sodimm.cfg
@@ -15,7 +15,7 @@ source [find target/at91sam9g45.cfg]
# Set reset type.
# reset_config trst_and_srst
-# adapter_nsrst_delay 200
+# adapter srst delay 200
# jtag_ntrst_delay 200
@@ -58,7 +58,7 @@ proc at91sam9g45_start { } {
arm7_9 fast_memory_access disable
# Slow-speed oscillator enabled at reset, so run jtag speed slow.
- adapter_khz 4
+ adapter speed 4
# Make sure processor is halted, or error will result in following steps.
halt
wait_halt 10000
@@ -117,7 +117,7 @@ proc at91sam9g45_init { } {
# Switch over to adaptive clocking.
- adapter_khz 6000
+ adapter speed 6000
# Enable faster DCC downloads.
diff --git a/tcl/board/imx27lnst.cfg b/tcl/board/imx27lnst.cfg
index e0ed057..ac5a9f3 100644
--- a/tcl/board/imx27lnst.cfg
+++ b/tcl/board/imx27lnst.cfg
@@ -8,7 +8,7 @@ proc imx27lnst_init { } {
# This setup puts RAM at 0xA0000000
# reset the board correctly
- adapter_khz 500
+ adapter speed 500
reset run
reset halt
diff --git a/tcl/board/imx53-m53evk.cfg b/tcl/board/imx53-m53evk.cfg
index eada27a..d18afc7 100644
--- a/tcl/board/imx53-m53evk.cfg
+++ b/tcl/board/imx53-m53evk.cfg
@@ -18,7 +18,7 @@ echo "iMX53 M53EVK board lodaded."
reset_config trst_and_srst separate trst_open_drain srst_open_drain
# Run at 6 MHz
-adapter_khz 6000
+adapter speed 6000
$_TARGETNAME configure -event "reset-assert" {
echo "Reseting ...."
diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg
index 06c3993..57473ea 100644
--- a/tcl/board/imx53loco.cfg
+++ b/tcl/board/imx53loco.cfg
@@ -13,7 +13,7 @@ echo "iMX53 Loco board lodaded."
# Set reset type
#reset_config srst_only
-adapter_khz 3000
+adapter speed 3000
# Slow speed to be sure it will work
jtag_rclk 1000
@@ -59,7 +59,7 @@ proc loco_init { } {
arm core_state arm
jtag_rclk 3000
-# adapter_khz 3000
+# adapter speed 3000
}
diff --git a/tcl/board/insignal_arndale.cfg b/tcl/board/insignal_arndale.cfg
index 25c123e..09a7223 100644
--- a/tcl/board/insignal_arndale.cfg
+++ b/tcl/board/insignal_arndale.cfg
@@ -5,4 +5,4 @@
source [find target/exynos5250.cfg]
# Experimentally determined highest working speed
-adapter_khz 200
+adapter speed 200
diff --git a/tcl/board/kasli.cfg b/tcl/board/kasli.cfg
index fb59f93..06cc1e6 100644
--- a/tcl/board/kasli.cfg
+++ b/tcl/board/kasli.cfg
@@ -7,7 +7,7 @@ ftdi_layout_init 0x0008 0x000b
reset_config none
transport select jtag
-adapter_khz 25000
+adapter speed 25000
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
diff --git a/tcl/board/kc705.cfg b/tcl/board/kc705.cfg
index e032e9b..51ea14d 100644
--- a/tcl/board/kc705.cfg
+++ b/tcl/board/kc705.cfg
@@ -5,7 +5,7 @@ source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
source [find fpga/xilinx-xadc.cfg]
source [find fpga/xilinx-dna.cfg]
-adapter_khz 25000
+adapter speed 25000
# example command to write bitstream, soft-cpu bios and runtime:
# openocd -f board/kc705.cfg -c "init;\
diff --git a/tcl/board/kcu105.cfg b/tcl/board/kcu105.cfg
index c8daea6..e2b68ca 100644
--- a/tcl/board/kcu105.cfg
+++ b/tcl/board/kcu105.cfg
@@ -8,4 +8,4 @@ source [find cpld/xilinx-xcu.cfg]
source [find cpld/jtagspi.cfg]
-adapter_khz 25000
+adapter speed 25000
diff --git a/tcl/board/kindle2.cfg b/tcl/board/kindle2.cfg
index f32b2a3..fbb1022 100644
--- a/tcl/board/kindle2.cfg
+++ b/tcl/board/kindle2.cfg
@@ -18,7 +18,7 @@ source [find target/imx31.cfg]
source [find target/imx.cfg]
$_TARGETNAME configure -event reset-init { kindle2_init }
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
# 8MiB NOR Flash
set _FLASHNAME $_CHIPNAME.flash
@@ -36,7 +36,7 @@ jtag_ntrst_delay 30
# this is broken but enabled by default
arm11 memwrite burst disable
-adapter_khz 1000
+adapter speed 1000
ftdi_tdo_sample_edge falling
proc kindle2_init {} {
diff --git a/tcl/board/lubbock.cfg b/tcl/board/lubbock.cfg
index 298954c..d803e6f 100644
--- a/tcl/board/lubbock.cfg
+++ b/tcl/board/lubbock.cfg
@@ -4,7 +4,7 @@
source [find target/pxa255.cfg]
-adapter_nsrst_delay 250
+adapter srst delay 250
jtag_ntrst_delay 250
# NOTE: until after pinmux and such are set up, only CS0 is
diff --git a/tcl/board/marsohod.cfg b/tcl/board/marsohod.cfg
index 681f575..b1393a9 100644
--- a/tcl/board/marsohod.cfg
+++ b/tcl/board/marsohod.cfg
@@ -6,7 +6,7 @@
# Recommended MBFTDI programmer
source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
transport select jtag
# Altera MAXII EPM240T100C CPLD
diff --git a/tcl/board/marsohod2.cfg b/tcl/board/marsohod2.cfg
index d4897c3..31819a2 100644
--- a/tcl/board/marsohod2.cfg
+++ b/tcl/board/marsohod2.cfg
@@ -6,7 +6,7 @@
# Built-in MBFTDI programmer
source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
transport select jtag
# Cyclone III EP3C10E144 FPGA
diff --git a/tcl/board/marsohod3.cfg b/tcl/board/marsohod3.cfg
index bb3c74f..fa00706 100644
--- a/tcl/board/marsohod3.cfg
+++ b/tcl/board/marsohod3.cfg
@@ -6,7 +6,7 @@
# Built-in MBFTDI programmer
source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
transport select jtag
# MAX10 10M50SAE144C8GES FPGA
diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg
index 068a19b..4954dab 100644
--- a/tcl/board/mcb1700.cfg
+++ b/tcl/board/mcb1700.cfg
@@ -11,7 +11,7 @@ set MCB1700_CCLK $CCLK
$_TARGETNAME configure -event reset-start {
# Start *real slow* as we do not know the
# state the boot rom left the clock in
- adapter_khz 10
+ adapter speed 10
}
# Set up 100MHz clock to CPU
@@ -55,7 +55,7 @@ $_TARGETNAME configure -event reset-init {
#
#
global MCB1700_CCLK
- adapter_khz [expr $MCB1700_CCLK / 8]
+ adapter speed [expr $MCB1700_CCLK / 8]
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
diff --git a/tcl/board/microchip_saml11_xplained_pro.cfg \
b/tcl/board/microchip_saml11_xplained_pro.cfg index 3558a8e..2ab6111 100644
--- a/tcl/board/microchip_saml11_xplained_pro.cfg
+++ b/tcl/board/microchip_saml11_xplained_pro.cfg
@@ -4,7 +4,7 @@
#
source [find interface/cmsis-dap.cfg]
-adapter_khz 1000
+adapter speed 1000
set CHIPNAME saml11
source [find target/atsaml1x.cfg]
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index 874f829..9dca5a3 100644
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -111,7 +111,7 @@ target create $_TARGETNAME arm920t -endian $_ENDIAN \
-chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x40000000 \
-work-area-size 0x4000 -work-area-backup 1
#reset configuration
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
@@ -120,7 +120,7 @@ reset_config trst_and_srst
# IMPORTANT! See README at top of this file.
#-------------------------------------------------------------------------
- adapter_khz 12000
+ adapter speed 12000
jtag interface
#-------------------------------------------------------------------------
@@ -140,7 +140,7 @@ reset_config trst_and_srst
nand device s3c2440 0
- adapter_nsrst_delay 100
+ adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
init
diff --git a/tcl/board/mini6410.cfg b/tcl/board/mini6410.cfg
index d00ce1f..2cee939 100644
--- a/tcl/board/mini6410.cfg
+++ b/tcl/board/mini6410.cfg
@@ -88,8 +88,8 @@ proc init_6410_flash {} {
}
-adapter_khz 1000
-adapter_nsrst_delay 100
+adapter speed 1000
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
diff --git a/tcl/board/numato_mimas_a7.cfg b/tcl/board/numato_mimas_a7.cfg
index a538872..d4012ba 100644
--- a/tcl/board/numato_mimas_a7.cfg
+++ b/tcl/board/numato_mimas_a7.cfg
@@ -30,7 +30,7 @@ ftdi_tdo_sample_edge falling
#
ftdi_layout_init 0x0008 0x004b
reset_config none
-adapter_khz 30000
+adapter speed 30000
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
diff --git a/tcl/board/nxp_imx7sabre.cfg b/tcl/board/nxp_imx7sabre.cfg
index 25b7b87..c595e3a 100644
--- a/tcl/board/nxp_imx7sabre.cfg
+++ b/tcl/board/nxp_imx7sabre.cfg
@@ -3,12 +3,12 @@
transport select jtag
# set a safe speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
# reset configuration has TRST and SRST support
reset_config trst_and_srst srst_push_pull
# need at least 100ms delay after SRST release for JTAG
-adapter_nsrst_delay 100
+adapter srst delay 100
# source the target file
source [find target/imx7.cfg]
diff --git a/tcl/board/nxp_mcimx8m-evk.cfg b/tcl/board/nxp_mcimx8m-evk.cfg
index e2d63ce..dd9bd53 100644
--- a/tcl/board/nxp_mcimx8m-evk.cfg
+++ b/tcl/board/nxp_mcimx8m-evk.cfg
@@ -6,13 +6,13 @@
transport select jtag
# set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
# default JTAG configuration has only SRST and no TRST
reset_config srst_only srst_push_pull
# delay after SRST goes inactive
-adapter_nsrst_delay 70
+adapter srst delay 70
# board has an i.MX8MQ with 4 Cortex-A53 cores
set CHIPNAME imx8mq
diff --git a/tcl/board/olimex_sam7_la2.cfg b/tcl/board/olimex_sam7_la2.cfg
index 89d2b5a..038fe67 100644
--- a/tcl/board/olimex_sam7_la2.cfg
+++ b/tcl/board/olimex_sam7_la2.cfg
@@ -2,7 +2,7 @@ source [find target/at91sam7a2.cfg]
# delays needed to get stable reads of cpu state
jtag_ntrst_delay 10
-adapter_nsrst_delay 200
+adapter srst delay 200
# board uses pullup and connects only srst
reset_config srst_open_drain
@@ -10,9 +10,9 @@ reset_config srst_open_drain
# srst is connected to NRESET of CPU and fully resets everything...
reset_config srst_only srst_pulls_trst
-adapter_khz 1
+adapter speed 1
$_TARGETNAME configure -event reset-start {
- adapter_khz 1
+ adapter speed 1
}
$_TARGETNAME configure -event reset-init {
@@ -61,7 +61,7 @@ $_TARGETNAME configure -event reset-init {
echo "set up pll"
sleep 100
- adapter_khz 5000
+ adapter speed 5000
}
$_TARGETNAME arm7_9 dcc_downloads enable
diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index db3cb03..eda4392 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -3,7 +3,7 @@
source [find interface/ftdi/openrd.cfg]
source [find target/feroceon.cfg]
-adapter_khz 2000
+adapter speed 2000
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
diff --git a/tcl/board/or1k_generic.cfg b/tcl/board/or1k_generic.cfg
index c543ebe..7c19565 100644
--- a/tcl/board/or1k_generic.cfg
+++ b/tcl/board/or1k_generic.cfg
@@ -17,7 +17,7 @@ source [find target/or1k.cfg]
poll_period 1
# Set the adapter speed
-adapter_khz 3000
+adapter speed 3000
# Enable the target description feature
gdb_target_description enable
diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg
index 6a7e8e9..1c48f5d 100644
--- a/tcl/board/phytec_lpc3250.cfg
+++ b/tcl/board/phytec_lpc3250.cfg
@@ -1,8 +1,8 @@
source [find target/lpc3250.cfg]
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 1
-adapter_khz 200
+adapter speed 200
reset_config trst_and_srst separate
arm7_9 dcc_downloads enable
@@ -11,11 +11,11 @@ $_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-start {
arm7_9 fast_memory_access disable
- adapter_khz 200
+ adapter speed 200
}
$_TARGETNAME configure -event reset-end {
- adapter_khz 6000
+ adapter speed 6000
arm7_9 fast_memory_access enable
}
diff --git a/tcl/board/pxa255_sst.cfg b/tcl/board/pxa255_sst.cfg
index 49cad5d..2b44a05 100644
--- a/tcl/board/pxa255_sst.cfg
+++ b/tcl/board/pxa255_sst.cfg
@@ -93,7 +93,7 @@ $_TARGETNAME configure -event reset-init {pxa255_sst_init}
reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
#xscale debug_handler 0 0xFFFF0800 ;# debug handler base address
diff --git a/tcl/board/quark_d2000_refboard.cfg b/tcl/board/quark_d2000_refboard.cfg
index 460e8c9..8b8314a 100644
--- a/tcl/board/quark_d2000_refboard.cfg
+++ b/tcl/board/quark_d2000_refboard.cfg
@@ -10,6 +10,6 @@ ftdi_layout_signal nTRST -data 0x0100 -noe 0x0100
source [find target/quark_d20xx.cfg]
-adapter_khz 1000
+adapter speed 1000
reset_config trst_only
diff --git a/tcl/board/quark_x10xx_board.cfg b/tcl/board/quark_x10xx_board.cfg
index 8dc600b..4ecf30e 100644
--- a/tcl/board/quark_x10xx_board.cfg
+++ b/tcl/board/quark_x10xx_board.cfg
@@ -4,6 +4,6 @@
source [find target/quark_x10xx.cfg]
#default frequency but this can be adjusted at runtime
-adapter_khz 4000
+adapter speed 4000
reset_config trst_only
diff --git a/tcl/board/rsc-w910.cfg b/tcl/board/rsc-w910.cfg
index 636a053..cb1733b 100644
--- a/tcl/board/rsc-w910.cfg
+++ b/tcl/board/rsc-w910.cfg
@@ -12,8 +12,8 @@ source [find target/nuc910.cfg]
#
reset_config trst_and_srst srst_pulls_trst
-adapter_khz 1000
-adapter_nsrst_delay 100
+adapter speed 1000
+adapter srst delay 100
jtag_ntrst_delay 100
$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 \
-work-area-backup 0 @@ -28,7 +28,7 @@ nand device $_NANDNAME nuc910 $_TARGETNAME
# Target events
#
-$_TARGETNAME configure -event reset-start {adapter_khz 1000}
+$_TARGETNAME configure -event reset-start {adapter speed 1000}
$_TARGETNAME configure -event reset-init {
# switch on PLL for 200MHz operation
@@ -47,7 +47,7 @@ $_TARGETNAME configure -event reset-init {
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
- adapter_khz 15000
+ adapter speed 15000
# map nor flash to 0x20000000
# map sdram to 0x00000000
diff --git a/tcl/board/sayma_amc.cfg b/tcl/board/sayma_amc.cfg
index 0b507ee..009eb78 100644
--- a/tcl/board/sayma_amc.cfg
+++ b/tcl/board/sayma_amc.cfg
@@ -26,7 +26,7 @@ ftdi_layout_init 0x0098 0x008b
#ftdi_layout_signal nTRST -data 0x0010
reset_config none
-adapter_khz 5000
+adapter speed 5000
transport select jtag
diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg
index ff333ca..c00dc91 100644
--- a/tcl/board/sheevaplug.cfg
+++ b/tcl/board/sheevaplug.cfg
@@ -3,7 +3,7 @@
source [find interface/ftdi/sheevaplug.cfg]
source [find target/feroceon.cfg]
-adapter_khz 2000
+adapter speed 2000
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
diff --git a/tcl/board/sifive-e31arty.cfg b/tcl/board/sifive-e31arty.cfg
index ec10b27..b7a255e 100644
--- a/tcl/board/sifive-e31arty.cfg
+++ b/tcl/board/sifive-e31arty.cfg
@@ -1,7 +1,7 @@
#
# Be sure you include the speed and interface before this file
# Example:
-# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f \
"board/sifive-e31arty.cfg" +# -c "adapter speed 5000" -f \
"interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg"
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
diff --git a/tcl/board/sifive-e51arty.cfg b/tcl/board/sifive-e51arty.cfg
index ffd83a0..20ad575 100644
--- a/tcl/board/sifive-e51arty.cfg
+++ b/tcl/board/sifive-e51arty.cfg
@@ -1,7 +1,7 @@
#
# Be sure you include the speed and interface before this file
# Example:
-# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f \
"board/sifive-e51arty.cfg" +# -c "adapter speed 5000" -f \
"interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg"
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
diff --git a/tcl/board/sifive-hifive1.cfg b/tcl/board/sifive-hifive1.cfg
index 9e62bbd..196f540 100644
--- a/tcl/board/sifive-hifive1.cfg
+++ b/tcl/board/sifive-hifive1.cfg
@@ -1,4 +1,4 @@
-adapter_khz 10000
+adapter speed 10000
adapter driver ftdi
ftdi_device_desc "Dual RS232-HS"
@@ -10,7 +10,7 @@ ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
#Reset Stretcher logic on FE310 is ~1 second long
#This doesn't apply if you use
# ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
+#adapter srst delay 1500
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
diff --git a/tcl/board/telo.cfg b/tcl/board/telo.cfg
index 1d3afdf..05644f6 100644
--- a/tcl/board/telo.cfg
+++ b/tcl/board/telo.cfg
@@ -10,10 +10,10 @@ source [find target/c100helper.tcl]
# Telo board & C100 support trst and srst
# make the reset asserted to
# allow RC circuit to discharge for: [ms]
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
jtag_ntrst_assert_width 100
# don't talk to JTAG after reset for: [ms]
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst separate
@@ -23,11 +23,11 @@ reset_config trst_and_srst separate
# issue telnet: reset init
# issue gdb: monitor reset init
$_TARGETNAME configure -event reset-init {
- adapter_khz 100
+ adapter speed 100
# this will setup Telo board
setupTelo
#turn up the JTAG speed
- adapter_khz 3000
+ adapter speed 3000
echo "JTAG speek now 3MHz"
echo "type helpC100 to get help on C100"
}
diff --git a/tcl/board/ti_am437x_idk.cfg b/tcl/board/ti_am437x_idk.cfg
index 65e2094..fc2b81b 100644
--- a/tcl/board/ti_am437x_idk.cfg
+++ b/tcl/board/ti_am437x_idk.cfg
@@ -4,7 +4,7 @@
source [find interface/ftdi/xds100v2.cfg]
transport select jtag
-adapter_khz 30000
+adapter speed 30000
source [find target/am437x.cfg]
$_TARGETNAME configure -event reset-init { init_platform 0x61a11b32 }
diff --git a/tcl/board/ti_am43xx_evm.cfg b/tcl/board/ti_am43xx_evm.cfg
index d536314..dbc37ae 100644
--- a/tcl/board/ti_am43xx_evm.cfg
+++ b/tcl/board/ti_am43xx_evm.cfg
@@ -1,6 +1,6 @@
# Works on both AM437x GP EVM and AM438x ePOS EVM
transport select jtag
-adapter_khz 16000
+adapter speed 16000
source [find target/am437x.cfg]
diff --git a/tcl/board/ti_beaglebone.cfg b/tcl/board/ti_beaglebone.cfg
index a54ad62..6a6272d 100644
--- a/tcl/board/ti_beaglebone.cfg
+++ b/tcl/board/ti_beaglebone.cfg
@@ -4,7 +4,7 @@
# The JTAG interface is built directly on the board.
source [find interface/ftdi/xds100v2.cfg]
-adapter_khz 16000
+adapter speed 16000
reset_config trst_and_srst
diff --git a/tcl/board/ti_beaglebone_black.cfg b/tcl/board/ti_beaglebone_black.cfg
index 79fc1e8..c730814 100644
--- a/tcl/board/ti_beaglebone_black.cfg
+++ b/tcl/board/ti_beaglebone_black.cfg
@@ -1,7 +1,7 @@
# AM335x Beaglebone Black
# http://beagleboard.org/bone
-adapter_khz 1000
+adapter speed 1000
reset_config trst_and_srst
diff --git a/tcl/board/ti_cc13x0_launchpad.cfg b/tcl/board/ti_cc13x0_launchpad.cfg
index 9e1c1ea..d2d0c68 100644
--- a/tcl/board/ti_cc13x0_launchpad.cfg
+++ b/tcl/board/ti_cc13x0_launchpad.cfg
@@ -3,5 +3,5 @@
#
source [find interface/xds110.cfg]
transport select jtag
-adapter_khz 2500
+adapter speed 2500
source [find target/ti_cc13x0.cfg]
diff --git a/tcl/board/ti_cc13x2_launchpad.cfg b/tcl/board/ti_cc13x2_launchpad.cfg
index 18c5ce5..706bb72 100644
--- a/tcl/board/ti_cc13x2_launchpad.cfg
+++ b/tcl/board/ti_cc13x2_launchpad.cfg
@@ -2,6 +2,6 @@
# TI CC13x2 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select jtag
source [find target/ti_cc13x2.cfg]
diff --git a/tcl/board/ti_cc26x0_launchpad.cfg b/tcl/board/ti_cc26x0_launchpad.cfg
index 3613a47..c16fa4c 100644
--- a/tcl/board/ti_cc26x0_launchpad.cfg
+++ b/tcl/board/ti_cc26x0_launchpad.cfg
@@ -2,6 +2,6 @@
# TI CC26x0 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select jtag
source [find target/ti_cc26x0.cfg]
diff --git a/tcl/board/ti_cc26x2_launchpad.cfg b/tcl/board/ti_cc26x2_launchpad.cfg
index 2f2b34b..e794191 100644
--- a/tcl/board/ti_cc26x2_launchpad.cfg
+++ b/tcl/board/ti_cc26x2_launchpad.cfg
@@ -2,6 +2,6 @@
# TI CC26x2 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select jtag
source [find target/ti_cc26x2.cfg]
diff --git a/tcl/board/ti_cc3200_launchxl.cfg b/tcl/board/ti_cc3200_launchxl.cfg
index b78b09b..34f9bff 100644
--- a/tcl/board/ti_cc3200_launchxl.cfg
+++ b/tcl/board/ti_cc3200_launchxl.cfg
@@ -12,7 +12,7 @@ if { [info exists TRANSPORT] } {
transport select jtag
}
-adapter_khz 2500
+adapter speed 2500
set WORKAREASIZE 0x40000
source [find target/ti_cc32xx.cfg]
diff --git a/tcl/board/ti_cc3220sf_launchpad.cfg \
b/tcl/board/ti_cc3220sf_launchpad.cfg index a3dac62..30255c7 100644
--- a/tcl/board/ti_cc3220sf_launchpad.cfg
+++ b/tcl/board/ti_cc3220sf_launchpad.cfg
@@ -2,6 +2,6 @@
# TI CC3220SF-LaunchXL LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select swd
source [find target/ti_cc3220sf.cfg]
diff --git a/tcl/board/ti_cc32xx_launchpad.cfg b/tcl/board/ti_cc32xx_launchpad.cfg
index f657bdf..6676e5d 100644
--- a/tcl/board/ti_cc32xx_launchpad.cfg
+++ b/tcl/board/ti_cc32xx_launchpad.cfg
@@ -2,6 +2,6 @@
# TI CC32xx-LaunchXL LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select swd
source [find target/ti_cc32xx.cfg]
diff --git a/tcl/board/ti_msp432_launchpad.cfg b/tcl/board/ti_msp432_launchpad.cfg
index bfad322..f7c96ee 100644
--- a/tcl/board/ti_msp432_launchpad.cfg
+++ b/tcl/board/ti_msp432_launchpad.cfg
@@ -2,6 +2,6 @@
# TI MSP432 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select swd
source [find target/ti_msp432.cfg]
diff --git a/tcl/board/ti_tmdx570ls31usb.cfg b/tcl/board/ti_tmdx570ls31usb.cfg
index 5502444..6d73502 100644
--- a/tcl/board/ti_tmdx570ls31usb.cfg
+++ b/tcl/board/ti_tmdx570ls31usb.cfg
@@ -1,4 +1,4 @@
-adapter_khz 1500
+adapter speed 1500
source [find interface/ftdi/xds100v2.cfg]
source [find target/ti_tms570.cfg]
diff --git a/tcl/board/tocoding_poplar.cfg b/tcl/board/tocoding_poplar.cfg
index d8b8330..d0951ce 100644
--- a/tcl/board/tocoding_poplar.cfg
+++ b/tcl/board/tocoding_poplar.cfg
@@ -5,7 +5,7 @@
# board does not feature anything but JTAG
transport select jtag
-adapter_khz 10000
+adapter speed 10000
# SRST-only reset configuration
reset_config srst_only srst_push_pull
diff --git a/tcl/board/topas910.cfg b/tcl/board/topas910.cfg
index 90c18c4..77084a9 100644
--- a/tcl/board/topas910.cfg
+++ b/tcl/board/topas910.cfg
@@ -99,7 +99,7 @@ proc topas910_init { } {
mww 0xf4300004 0x00000000
sleep 10
-# adapter_khz NNNN
+# adapter speed NNNN
# remap off in case of IROM boot
mww 0xf0000004 0x00000001
diff --git a/tcl/board/topasa900.cfg b/tcl/board/topasa900.cfg
index 2a388d5..91ee584 100644
--- a/tcl/board/topasa900.cfg
+++ b/tcl/board/topasa900.cfg
@@ -105,7 +105,7 @@ proc topasa900_init { } {
mww 0xf4300004 0x00000000
sleep 10
-# adapter_khz NNNN
+# adapter speed NNNN
# remap off in case of IROM boot
mww 0xf0000004 0x00000001
diff --git a/tcl/board/twr-vf65gs10.cfg b/tcl/board/twr-vf65gs10.cfg
index a80407f..0d6d332 100644
--- a/tcl/board/twr-vf65gs10.cfg
+++ b/tcl/board/twr-vf65gs10.cfg
@@ -198,4 +198,4 @@ proc board_init { } {
# hook the init function into the reset-init event
${_TARGETNAME}0 configure -event reset-init { board_init }
# set a slow default JTAG clock, can be overridden later
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/board/verdex.cfg b/tcl/board/verdex.cfg
index 6da9875..dd267fc 100644
--- a/tcl/board/verdex.cfg
+++ b/tcl/board/verdex.cfg
@@ -8,7 +8,7 @@ source [find target/pxa270.cfg]
reset_config trst_and_srst separate
# XM4 = 400MHz, XL6P = 600MHz...let's run at 0.1*400MHz=40MHz
-adapter_khz 40000
+adapter speed 40000
# flash bank <driver> <base> <size> <chip_width> <bus_width>
# XL6P has 32 MB flash
diff --git a/tcl/board/voltcraft_dso-3062c.cfg b/tcl/board/voltcraft_dso-3062c.cfg
index 01e37e9..01879b1 100644
--- a/tcl/board/voltcraft_dso-3062c.cfg
+++ b/tcl/board/voltcraft_dso-3062c.cfg
@@ -13,7 +13,7 @@
source [find target/samsung_s3c2440.cfg]
-adapter_khz 16000
+adapter speed 16000
# Samsung K9F1208U0C NAND flash chip (64MiB, 3.3V, 8-bit)
nand device $_CHIPNAME.nand s3c2440 $_TARGETNAME
diff --git a/tcl/board/zy1000.cfg b/tcl/board/zy1000.cfg
index 57deaa8..e0d1ccf 100644
--- a/tcl/board/zy1000.cfg
+++ b/tcl/board/zy1000.cfg
@@ -72,7 +72,7 @@ $_TARGETNAME configure -event gdb-attach {
# other things than flash programming.
$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x20000 \
-work-area-backup 0
-adapter_khz 16000
+adapter speed 16000
proc production_info {} {
diff --git a/tcl/interface/calao-usb-a9260.cfg b/tcl/interface/calao-usb-a9260.cfg
index 5fae2f3..d1dc736 100644
--- a/tcl/interface/calao-usb-a9260.cfg
+++ b/tcl/interface/calao-usb-a9260.cfg
@@ -6,6 +6,6 @@
# See calao-usb-a9260-c01.cfg and calao-usb-a9260-c02.cfg.
#
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
diff --git a/tcl/interface/ft232r.cfg b/tcl/interface/ft232r.cfg
index 24e338f..2c705c3 100644
--- a/tcl/interface/ft232r.cfg
+++ b/tcl/interface/ft232r.cfg
@@ -1,2 +1,2 @@
adapter driver ft232r
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/interface/ftdi/minispartan6.cfg \
b/tcl/interface/ftdi/minispartan6.cfg index 92aebbc..97a6abe 100644
--- a/tcl/interface/ftdi/minispartan6.cfg
+++ b/tcl/interface/ftdi/minispartan6.cfg
@@ -12,4 +12,4 @@ ftdi_layout_init 0x0008 0x000b
reset_config none
# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
-adapter_khz 30000
+adapter speed 30000
diff --git a/tcl/interface/ftdi/pipistrello.cfg b/tcl/interface/ftdi/pipistrello.cfg
index 4e39294..2074924 100644
--- a/tcl/interface/ftdi/pipistrello.cfg
+++ b/tcl/interface/ftdi/pipistrello.cfg
@@ -10,4 +10,4 @@ ftdi_layout_init 0x0008 0x000b
reset_config none
# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
-adapter_khz 10000
+adapter speed 10000
diff --git a/tcl/interface/nds32-aice.cfg b/tcl/interface/nds32-aice.cfg
index 8f32c89..3b21025 100644
--- a/tcl/interface/nds32-aice.cfg
+++ b/tcl/interface/nds32-aice.cfg
@@ -10,6 +10,6 @@ aice serial "C001-42163"
aice vid_pid 0x1CFC 0x0000
aice port aice_usb
reset_config trst_and_srst
-adapter_khz 24000
+adapter speed 24000
aice retry_times 50
aice count_to_check_dbger 30
diff --git "a/tcl/target/1986\320\262\320\2651\321\202.cfg" \
"b/tcl/target/1986\320\262\320\2651\321\202.cfg" index ecb3f8a..b7c9d63 100644
--- "a/tcl/target/1986\320\262\320\2651\321\202.cfg"
+++ "b/tcl/target/1986\320\262\320\2651\321\202.cfg"
@@ -50,9 +50,9 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
}
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
diff --git a/tcl/target/aduc702x.cfg b/tcl/target/aduc702x.cfg
index fca0a7f..9c756be 100644
--- a/tcl/target/aduc702x.cfg
+++ b/tcl/target/aduc702x.cfg
@@ -17,7 +17,7 @@ if { [info exists CPUTAPID] } {
set _CPUTAPID 0x3f0f0f0f
}
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
## JTAG scan chain
diff --git a/tcl/target/aducm360.cfg b/tcl/target/aducm360.cfg
index ca4bc68..caee965 100755
--- a/tcl/target/aducm360.cfg
+++ b/tcl/target/aducm360.cfg
@@ -36,7 +36,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_CPU dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# SWD/JTAG speed
-adapter_khz 1000
+adapter speed 1000
##
## Target configuration
@@ -51,6 +51,6 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size \
$_WORKAREASIZE set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME
-adapter_nsrst_delay 100
+adapter srst delay 100
cortex_m reset_config sysresetreq
diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg
index 32fd188..d8d78bd 100644
--- a/tcl/target/allwinner_v3s.cfg
+++ b/tcl/target/allwinner_v3s.cfg
@@ -34,7 +34,7 @@
# 0220ms JTAG pins switched to SD mode
#
# The time frame of 20ms can be not enough to init and halt the CPU. In this
-# case I would recommend to set: "adapter_khz 15000"
+# case I would recommend to set: "adapter speed 15000"
# To get more or less precise timings, the board should provide reset pin,
# or some bench power supply with remote function. In my case I used
# EEZ H24005 with this command to power on and halt the target:
diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg
index 9a83b5c..0fc8d67 100644
--- a/tcl/target/altera_fpgasoc.cfg
+++ b/tcl/target/altera_fpgasoc.cfg
@@ -36,7 +36,7 @@ jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask \
0x3 -expected- # core 1 - 0x80112000
# Slow speed to be sure it will work
-adapter_khz 1000
+adapter speed 1000
set _TARGETNAME1 $_CHIPNAME.cpu.0
set _TARGETNAME2 $_CHIPNAME.cpu.1
@@ -46,7 +46,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80110000
-$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
+$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
@@ -54,7 +54,7 @@ $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit \
$_TARGETNAME1" #target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
# -coreid 1 -dbgbase 0x80112000
-#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
+#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
proc cycv_dbginit {target} {
diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index 5c4e315..7098adf 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -45,7 +45,7 @@ if { [info exists CHIPTYPE] } {
# Run the adapter at the fastest acceptable speed with the slowest possible
# core clock.
-adapter_khz 10
+adapter speed 10
###############################################################################
# JTAG setup
@@ -157,7 +157,7 @@ $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size \
0x4000 # slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
# *after* PLL and clock tree setup.
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
+$_TARGETNAME configure -event "reset-start" { adapter speed 10 }
# Describe the reset assert process for openocd - this is asserted with the
# ICEPick
@@ -176,7 +176,7 @@ $_TARGETNAME configure -event reset-assert-post {
global _TARGETNAME
amdm37x_dbginit $_TARGETNAME
- adapter_khz 1000
+ adapter speed 1000
}
$_TARGETNAME configure -event gdb-attach {
diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg
index 196b048..0c64a96 100644
--- a/tcl/target/ar71xx.cfg
+++ b/tcl/target/ar71xx.cfg
@@ -1,7 +1,7 @@
# Atheros AR71xx MIPS 24Kc SoC.
# tested on PB44 refererence board
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg
index e7dec4b..7d01ccd 100644
--- a/tcl/target/at91sam3XXX.cfg
+++ b/tcl/target/at91sam3XXX.cfg
@@ -74,9 +74,9 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 500
+adapter speed 500
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg
index ff73670..ebb7eed 100644
--- a/tcl/target/at91sam4XXX.cfg
+++ b/tcl/target/at91sam4XXX.cfg
@@ -50,9 +50,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size \
$_WORKAREASIZE # running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 500
+adapter speed 500
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg
index 4aee7d0..b73babc 100644
--- a/tcl/target/at91sam4lXX.cfg
+++ b/tcl/target/at91sam4lXX.cfg
@@ -21,7 +21,7 @@ reset_config srst_gates_jtag
# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ \
SYSCLK/2 # but your mileage may vary.
-adapter_khz 50
+adapter speed 50
# System RC oscillator RCSYS starts in 3 cycles
-adapter_nsrst_delay 0
+adapter srst delay 0
diff --git a/tcl/target/at91sam9.cfg b/tcl/target/at91sam9.cfg
index bf99fb2..e0ea316 100644
--- a/tcl/target/at91sam9.cfg
+++ b/tcl/target/at91sam9.cfg
@@ -24,10 +24,10 @@ reset_config trst_and_srst separate trst_push_pull \
srst_open_drain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id \
$_CPUTAPID
-adapter_nsrst_delay 300
+adapter srst delay 300
jtag_ntrst_delay 200
-adapter_khz 3
+adapter speed 3
######################
# Target configuration
diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg \
b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg index 9ab7409..3e4b7d7 100644
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -6,15 +6,15 @@ source [find target/at91sam9261.cfg]
reset_config trst_and_srst
-adapter_khz 4
+adapter speed 4
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
scan_chain
$_TARGETNAME configure -event reset-start {
# at reset chip runs at 32khz
- adapter_khz 8
+ adapter speed 8
}
$_TARGETNAME configure -event reset-init {at91sam_init}
@@ -46,7 +46,7 @@ proc at91sam_init { } {
sleep 10 ;# wait 10 ms
# Now run at anything fast... ie: 10mhz!
- adapter_khz 10000 ;# Increase JTAG Speed to 6 MHz
+ adapter speed 10000 ;# Increase JTAG Speed to 6 MHz
mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash \
JS28F128P30T85 128MBit mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0
diff --git a/tcl/target/at91sam9g20.cfg b/tcl/target/at91sam9g20.cfg
index 3f5e3c6..6e45df2 100644
--- a/tcl/target/at91sam9g20.cfg
+++ b/tcl/target/at91sam9g20.cfg
@@ -12,7 +12,7 @@ source [find target/at91sam9.cfg]
# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz \
slow clock).
-adapter_khz 5
+adapter speed 5
# Establish internal SRAM memory work areas that are important to pre-bootstrap \
loaders, etc. The # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and \
the other starting at 0x00300000.
diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg
index f0644d1..9a396fa 100644
--- a/tcl/target/at91samdXX.cfg
+++ b/tcl/target/at91samdXX.cfg
@@ -66,12 +66,12 @@ reset_config srst_gates_jtag
# This limit is most probably imposed by incorrectly handled SWD WAIT
# on some SWD adapters.
-adapter_khz 400
+adapter speed 400
# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
# without problem at maximal clock speed. Atmel recommends
# adapter speed less than 10 * CPU clock.
-# adapter_khz 5000
+# adapter speed 5000
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg
index bea37ed..6ab238c 100644
--- a/tcl/target/atheros_ar9331.cfg
+++ b/tcl/target/atheros_ar9331.cfg
@@ -41,12 +41,12 @@ reset_config none srst_pulls_trst
# For SRST based variant we still need proper timings.
# For ETH part the reset should be asserted at least for 10ms
# Since there is no other information let's take 100ms to be sure.
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
# according to the SoC documentation it should take at least 5ms from
# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
# to live.
-adapter_nsrst_delay 8
+adapter srst delay 8
if { [info exists CHIPNAME] } {
set _CHIPNAME $_CHIPNAME
diff --git a/tcl/target/atmega128.cfg b/tcl/target/atmega128.cfg
index b8f7d01..07161d5 100644
--- a/tcl/target/atmega128.cfg
+++ b/tcl/target/atmega128.cfg
@@ -4,10 +4,10 @@
set _ENDIAN little
# jtag speed
-adapter_khz 4500
+adapter speed 4500
reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
#jtag scan chain
if { [info exists CPUTAPID] } {
@@ -27,7 +27,7 @@ flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
#to use it, script will be like:
#init
-#adapter_khz 4500
+#adapter speed 4500
#reset init
#verify_ircapture disable
#
diff --git a/tcl/target/atmega128rfa1.cfg b/tcl/target/atmega128rfa1.cfg
index 2c12a61..cda439d 100644
--- a/tcl/target/atmega128rfa1.cfg
+++ b/tcl/target/atmega128rfa1.cfg
@@ -2,7 +2,7 @@ set _CHIPNAME avr
set _ENDIAN little
# jtag speed
-adapter_khz 4500
+adapter speed 4500
# avr jtag docs never connect RSTN
reset_config none
diff --git a/tcl/target/atsame5x.cfg b/tcl/target/atsame5x.cfg
index 61949cf..351a2ca 100644
--- a/tcl/target/atsame5x.cfg
+++ b/tcl/target/atsame5x.cfg
@@ -63,7 +63,7 @@ reset_config srst_gates_jtag
# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
# without problem at clock speed over 5000 khz. Atmel recommends
# adapter speed less than 10 * CPU clock.
-adapter_khz 2000
+adapter speed 2000
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg
index 43962de..4c136ea 100644
--- a/tcl/target/atsamv.cfg
+++ b/tcl/target/atsamv.cfg
@@ -39,7 +39,7 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap \
$_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE \
-work-area-backup 0
-adapter_khz 1800
+adapter speed 1800
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/avr32.cfg b/tcl/target/avr32.cfg
index f5ee1a4..7808127 100644
--- a/tcl/target/avr32.cfg
+++ b/tcl/target/avr32.cfg
@@ -3,7 +3,7 @@ set _ENDIAN big
set _CPUTAPID 0x21e8203f
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst separate
diff --git a/tcl/target/bcm6348.cfg b/tcl/target/bcm6348.cfg
index 2540b51..a9be559 100644
--- a/tcl/target/bcm6348.cfg
+++ b/tcl/target/bcm6348.cfg
@@ -1,7 +1,7 @@
set _CHIPNAME bcm6348
set _CPUID 0x0634817f
-adapter_khz 1000
+adapter speed 1000
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg
index b0dd61a..109db17 100644
--- a/tcl/target/bluenrg-x.cfg
+++ b/tcl/target/bluenrg-x.cfg
@@ -20,7 +20,7 @@ if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE 0x5F00
}
-adapter_khz 4000
+adapter speed 4000
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg
index 1eaa8fe..5b4354e 100644
--- a/tcl/target/c100.cfg
+++ b/tcl/target/c100.cfg
@@ -3,7 +3,7 @@
# this script only configures one core (that is used to run Linux)
# assume no PLL lock, start slowly
-adapter_khz 100
+adapter speed 100
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index c9124cb..9da3730 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -491,7 +491,7 @@ proc reboot {} {
mww $TIMER_WDT_HIGH_BOUND 0xffffff
mww $TIMER_WDT_CURRENT_COUNT 0x0
echo "JTAG speed lowered to 100kHz"
- adapter_khz 100
+ adapter speed 100
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
echo -n "Wating for watchdog to trigger..."
diff --git a/tcl/target/cc2538.cfg b/tcl/target/cc2538.cfg
index 63fd9c2..8d232f4 100755
--- a/tcl/target/cc2538.cfg
+++ b/tcl/target/cc2538.cfg
@@ -1,7 +1,7 @@
# Config for Texas Instruments low power RF SoC CC2538
# http://www.ti.com/lit/pdf/swru319
-adapter_khz 100
+adapter speed 100
source [find target/icepick.cfg]
source [find target/ti-cjtag.cfg]
diff --git a/tcl/target/dragonite.cfg b/tcl/target/dragonite.cfg
index 750fd64..1277cca 100644
--- a/tcl/target/dragonite.cfg
+++ b/tcl/target/dragonite.cfg
@@ -26,6 +26,6 @@ set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg
index 6f32223..0ac0ce8 100644
--- a/tcl/target/dsp56321.cfg
+++ b/tcl/target/dsp56321.cfg
@@ -21,7 +21,7 @@ if { [info exists CPUTAPID] } {
}
#jtag speed
-adapter_khz 4500
+adapter speed 4500
#has only srst
reset_config srst_only
diff --git a/tcl/target/dsp568013.cfg b/tcl/target/dsp568013.cfg
index 0c491fa..98110c2 100644
--- a/tcl/target/dsp568013.cfg
+++ b/tcl/target/dsp568013.cfg
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
}
#jtag speed
-adapter_khz 800
+adapter speed 800
reset_config srst_only
diff --git a/tcl/target/dsp568037.cfg b/tcl/target/dsp568037.cfg
index 01194d0..010d06f 100644
--- a/tcl/target/dsp568037.cfg
+++ b/tcl/target/dsp568037.cfg
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
}
#jtag speed
-adapter_khz 800
+adapter speed 800
reset_config srst_only
diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg
index e22ce5c..c789efc 100644
--- a/tcl/target/efm32.cfg
+++ b/tcl/target/efm32.cfg
@@ -34,7 +34,7 @@ if { [info exists CPUTAPID] } {
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id \
$_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-adapter_khz 1000
+adapter speed 1000
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
diff --git a/tcl/target/epc9301.cfg b/tcl/target/epc9301.cfg
index f186d37..252bbab 100644
--- a/tcl/target/epc9301.cfg
+++ b/tcl/target/epc9301.cfg
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id \
$_CPUTAPID
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
set _TARGETNAME $_CHIPNAME.cpu
diff --git a/tcl/target/esi32xx.cfg b/tcl/target/esi32xx.cfg
index d32af39..6be84ab 100644
--- a/tcl/target/esi32xx.cfg
+++ b/tcl/target/esi32xx.cfg
@@ -26,7 +26,7 @@ if { [info exists CACHEARCH] } {
$_TARGETNAME esirisc cache_arch $CACHEARCH
}
-adapter_khz 2000
+adapter speed 2000
reset_config none
diff --git a/tcl/target/feroceon.cfg b/tcl/target/feroceon.cfg
index 389576e..b934426 100644
--- a/tcl/target/feroceon.cfg
+++ b/tcl/target/feroceon.cfg
@@ -26,6 +26,6 @@ set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg
index a0610ce..376320e 100644
--- a/tcl/target/fm3.cfg
+++ b/tcl/target/fm3.cfg
@@ -22,7 +22,7 @@ if { [info exists CPUTAPID] } {
}
# delays on reset lines
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
@@ -45,7 +45,7 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
# 4MHz / 6 = 666kHz, so use 500
-adapter_khz 500
+adapter speed 500
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/fm4.cfg b/tcl/target/fm4.cfg
index b79634d..bfe7115 100644
--- a/tcl/target/fm4.cfg
+++ b/tcl/target/fm4.cfg
@@ -24,7 +24,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
-adapter_khz 500
+adapter speed 500
if {![using_hla]} {
cortex_m reset_config sysresetreq
diff --git a/tcl/target/gp326xxxa.cfg b/tcl/target/gp326xxxa.cfg
index feb7554..df42c44 100644
--- a/tcl/target/gp326xxxa.cfg
+++ b/tcl/target/gp326xxxa.cfg
@@ -33,11 +33,11 @@ $_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size \
0x8000 -work-a reset_config trst_and_srst srst_pulls_trst
# This delay is needed otherwise communication with the target would
# be unreliable
-adapter_nsrst_delay 100
+adapter srst delay 100
# Set the adapter speed ridiculously low just in case we are
# running off of a 32kHz clock
-adapter_khz 2
+adapter speed 2
proc gp32xxxa_halt_and_reset_control_registers {} {
# System control registers
@@ -57,7 +57,7 @@ proc gp32xxxa_halt_and_reset_control_registers {} {
# Set the adapter speed ridiculously low just in case we are
# running off of a 32kHz clock
- adapter_khz 2
+ adapter speed 2
# Disable any advanced features at this stage
arm7_9 dcc_downloads disable
@@ -86,7 +86,7 @@ proc gp32xxxa_halt_and_reset_control_registers {} {
# Now that we know that we are running at 48Mhz
# Increase JTAG speed and enable speed optimization features
- adapter_khz 5000
+ adapter speed 5000
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
}
diff --git a/tcl/target/imx28.cfg b/tcl/target/imx28.cfg
index 4cc3950..1fea3fa 100644
--- a/tcl/target/imx28.cfg
+++ b/tcl/target/imx28.cfg
@@ -4,7 +4,7 @@
reset_config trst_and_srst
#jtag nTRST and nSRST delay
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
if { [info exists CHIPNAME] } {
diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg
index ca63951..d850657 100644
--- a/tcl/target/imx31.cfg
+++ b/tcl/target/imx31.cfg
@@ -3,7 +3,7 @@
reset_config trst_and_srst srst_gates_jtag
-adapter_nsrst_delay 5
+adapter srst delay 5
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index f359346..2945334 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -75,7 +75,7 @@ proc imx6_dbginit {target} {
}
# Slow speed to be sure it will work
-adapter_khz 1000
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
diff --git a/tcl/target/is5114.cfg b/tcl/target/is5114.cfg
index 31f1aa1..1a06b09 100644
--- a/tcl/target/is5114.cfg
+++ b/tcl/target/is5114.cfg
@@ -23,7 +23,7 @@ if { [info exists CPUTAPID] } {
}
# jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
+adapter speed 16
reset_config trst_and_srst
@@ -38,9 +38,9 @@ jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
- adapter_khz 3000
+ adapter speed 3000
}
$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 \
-work-area-backup 1
diff --git a/tcl/target/k1921vk01t.cfg b/tcl/target/k1921vk01t.cfg
index 1a84021..926f3c7 100755
--- a/tcl/target/k1921vk01t.cfg
+++ b/tcl/target/k1921vk01t.cfg
@@ -40,9 +40,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size \
$_WORKAREASIZE
flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME
-adapter_khz 2000
+adapter speed 2000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
diff --git a/tcl/target/ke0x.cfg b/tcl/target/ke0x.cfg
index 8239400..b92721f 100644
--- a/tcl/target/ke0x.cfg
+++ b/tcl/target/ke0x.cfg
@@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size \
$_WORKAREASIZE set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
-adapter_khz 1000
+adapter speed 1000
reset_config srst_nogate
diff --git a/tcl/target/klx.cfg b/tcl/target/klx.cfg
index 5d9286a..36b6ed5 100644
--- a/tcl/target/klx.cfg
+++ b/tcl/target/klx.cfg
@@ -40,7 +40,7 @@ kinetis create_banks
# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
# specifies up to 1MHz for VLPR mode and up to 24MHz for run mode;
# Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency.
-adapter_khz 1000
+adapter speed 1000
reset_config srst_nogate
diff --git a/tcl/target/ks869x.cfg b/tcl/target/ks869x.cfg
index 0f6829c..78cc402 100644
--- a/tcl/target/ks869x.cfg
+++ b/tcl/target/ks869x.cfg
@@ -18,7 +18,7 @@ if { [info exists CPUTAPID] } {
set _CPUTAPID 0x00922f0f
}
-adapter_khz 6000
+adapter speed 6000
# jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id \
$_CPUTAPID
diff --git a/tcl/target/kx.cfg b/tcl/target/kx.cfg
index 73ee62a..0ff5b0c 100644
--- a/tcl/target/kx.cfg
+++ b/tcl/target/kx.cfg
@@ -41,7 +41,7 @@ set _FLASHNAME $_CHIPNAME.pflash
flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
kinetis create_banks
-adapter_khz 1000
+adapter speed 1000
reset_config srst_nogate
diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg
index 925a049..481dc8a 100644
--- a/tcl/target/lpc1850.cfg
+++ b/tcl/target/lpc1850.cfg
@@ -1,6 +1,6 @@
source [find target/swj-dp.tcl]
-adapter_khz 500
+adapter speed 500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg
index 1969e46..946d1ce 100644
--- a/tcl/target/lpc1xxx.cfg
+++ b/tcl/target/lpc1xxx.cfg
@@ -145,10 +145,10 @@ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || \
$_CHIPSERIES == "l # Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
-adapter_khz 10
+adapter speed 10
# delays on reset lines
-adapter_nsrst_delay 200
+adapter srst delay 200
if {[using_jtag]} {
jtag_ntrst_delay 200
}
diff --git a/tcl/target/lpc2xxx.cfg b/tcl/target/lpc2xxx.cfg
index 11f1c48..4c3394c 100644
--- a/tcl/target/lpc2xxx.cfg
+++ b/tcl/target/lpc2xxx.cfg
@@ -13,10 +13,10 @@ proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant \
workarea_size c reset_config trst_and_srst
# reset delays
- adapter_nsrst_delay 100
+ adapter srst delay 100
jtag_ntrst_delay 100
- adapter_khz $adapter_freq_khz
+ adapter speed $adapter_freq_khz
foreach i $cputapids {
append expected_ids "-expected-id " $i " "
diff --git a/tcl/target/lpc3131.cfg b/tcl/target/lpc3131.cfg
index 27c1f67..185c0aa 100644
--- a/tcl/target/lpc3131.cfg
+++ b/tcl/target/lpc3131.cfg
@@ -52,7 +52,7 @@ dict set lpc313x wdt 0x13002400
# Target configuration
##################################################################
-adapter_nsrst_delay 1000
+adapter srst delay 1000
jtag_ntrst_delay 0
set _TARGETNAME $_CHIPNAME.cpu
diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index 2b72884..0c6d0ff 100644
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -1,6 +1,6 @@
source [find target/swj-dp.tcl]
-adapter_khz 500
+adapter speed 500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc4370.cfg b/tcl/target/lpc4370.cfg
index 1374ef2..9db2b9e 100644
--- a/tcl/target/lpc4370.cfg
+++ b/tcl/target/lpc4370.cfg
@@ -2,7 +2,7 @@
# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
#
-adapter_khz 500
+adapter speed 500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc8nxx.cfg b/tcl/target/lpc8nxx.cfg
index b933290..1bc77b2 100644
--- a/tcl/target/lpc8nxx.cfg
+++ b/tcl/target/lpc8nxx.cfg
@@ -22,7 +22,7 @@ if {![using_hla]} {
# If srst is not fitted use SYSRESETREQ to perform a soft reset
cortex_m reset_config sysresetreq
}
-adapter_nsrst_delay 100
+adapter srst delay 100
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 \
-work-area-backup 0
diff --git a/tcl/target/ls1012a.cfg b/tcl/target/ls1012a.cfg
index 9a9e684..19d3e58 100644
--- a/tcl/target/ls1012a.cfg
+++ b/tcl/target/ls1012a.cfg
@@ -32,4 +32,4 @@ target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -dbgbase \
0x80410000 -cti
target smp $_TARGETNAME
-adapter_khz 2000
+adapter speed 2000
diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg
index 80cb25a..6187bb9 100644
--- a/tcl/target/max32620.cfg
+++ b/tcl/target/max32620.cfg
@@ -2,7 +2,7 @@
# www.maximintegrated.com
# adapter speed
-adapter_khz 4000
+adapter speed 4000
# reset pin configuration
reset_config srst_only
diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg
index 7182b23..159b360 100644
--- a/tcl/target/max32625.cfg
+++ b/tcl/target/max32625.cfg
@@ -2,7 +2,7 @@
# www.maximintegrated.com
# adapter speed
-adapter_khz 4000
+adapter speed 4000
# reset pin configuration
reset_config srst_only
diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg
index f23b0b6..fc7d11f 100644
--- a/tcl/target/max3263x.cfg
+++ b/tcl/target/max3263x.cfg
@@ -2,7 +2,7 @@
# www.maximintegrated.com
# adapter speed
-adapter_khz 4000
+adapter speed 4000
# reset pin configuration
reset_config srst_only
diff --git a/tcl/target/mc13224v.cfg b/tcl/target/mc13224v.cfg
index 27ac8c3..f756dd9 100644
--- a/tcl/target/mc13224v.cfg
+++ b/tcl/target/mc13224v.cfg
@@ -35,8 +35,8 @@ reset_config srst_only
jtag_ntrst_delay 200
# rclk hasn't been working well. This maybe the mc13224v or something else.
-#adapter_khz 2000
-adapter_khz 2000
+#adapter speed 2000
+adapter speed 2000
######################
# Target configuration
diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg
index 6748102..820d2dd 100644
--- a/tcl/target/mdr32f9q2i.cfg
+++ b/tcl/target/mdr32f9q2i.cfg
@@ -49,9 +49,9 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
}
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 4f24020..d51a50e 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -50,7 +50,7 @@ flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
# The chip should start up from internal 16Mhz RC, so setting adapter
# clock to 1Mhz should be OK
#
-adapter_khz 1000
+adapter speed 1000
proc enable_all_ram {} {
# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index c29adbd..00901bf 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -30,7 +30,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
-adapter_khz 1000
+adapter speed 1000
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE \
-work-area-backup 0
diff --git a/tcl/target/numicro.cfg b/tcl/target/numicro.cfg
index c42dfbc..73022df 100644
--- a/tcl/target/numicro.cfg
+++ b/tcl/target/numicro.cfg
@@ -48,7 +48,7 @@ set _FLASHNAME $_CHIPNAME.flash_config
flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
# set default SWCLK frequency
-adapter_khz 1000
+adapter speed 1000
# set default srst setting "none"
reset_config none
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 078d7f2..dcf7c51 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -63,8 +63,8 @@ proc omap3_dbginit {target} {
# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
-adapter_khz 1000
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg
index c4ff40e..2f9338b 100644
--- a/tcl/target/omap5912.cfg
+++ b/tcl/target/omap5912.cfg
@@ -14,7 +14,7 @@ if { [info exists CPUTAPID] } {
set _CPUTAPID 0x0692602f
}
-adapter_nsrst_delay 100
+adapter srst delay 100
# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for
# its standalone siblings (like TMS320VC5502) of the same era
diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index fd9ff4c..30cf23c 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -52,8 +52,8 @@ $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size \
0x2000 # be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index d53b99a..51a6bbd 100644
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -23,7 +23,7 @@ if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE 0x4000
}
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
#jtag scan chain
diff --git a/tcl/target/psoc4.cfg b/tcl/target/psoc4.cfg
index 544e109..b568282 100644
--- a/tcl/target/psoc4.cfg
+++ b/tcl/target/psoc4.cfg
@@ -36,7 +36,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size \
$_WORKAREASIZE set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
-adapter_khz 1500
+adapter speed 1500
# Reset, bloody PSoC 4 reset
#
@@ -118,7 +118,7 @@ proc ocd_process_reset_inner { MODE } {
}
if { ! [info exists PSOC4_USE_ACQUIRE] } {
- if { 0 == [string compare [adapter_name] kitprog ] } {
+ if { 0 == [string compare [adapter name] kitprog ] } {
set PSOC4_USE_ACQUIRE 1
} else {
set PSOC4_USE_ACQUIRE 0
@@ -138,7 +138,7 @@ proc ocd_process_reset_inner { MODE } {
$t invoke-event reset-assert-pre
if { $halt && $PSOC4_USE_ACQUIRE } {
- catch { [adapter_name] acquire_psoc }
+ catch { [adapter name] acquire_psoc }
$t arp_examine
} else {
if { $PSOC4_TEST_MODE_WORKAROUND } {
diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
index fc0c711..51d032b 100644
--- a/tcl/target/psoc6.cfg
+++ b/tcl/target/psoc6.cfg
@@ -6,7 +6,7 @@
source [find target/swj-dp.tcl]
-adapter_khz 1000
+adapter speed 1000
global _CHIPNAME
if { [info exists CHIPNAME] } {
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 3862425..62eaeec 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
# PXA255 comes out of reset using 3.6864 MHz oscillator.
# Until the PLL kicks in, keep the JTAG clock slow enough
# that we get no errors.
-adapter_khz 300
-$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
# both TRST and SRST are *required* for debug
# DCSR is often accessed with SRST active
diff --git a/tcl/target/pxa270.cfg b/tcl/target/pxa270.cfg
index 95f7f16..bd904b5 100644
--- a/tcl/target/pxa270.cfg
+++ b/tcl/target/pxa270.cfg
@@ -34,9 +34,9 @@ if { [info exists CPUTAPID3] } {
set _CPUTAPID3 0x89265013
}
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
+# set adapter srst delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
+adapter srst delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 250
diff --git a/tcl/target/pxa3xx.cfg b/tcl/target/pxa3xx.cfg
index c459f6e..1a4539c 100644
--- a/tcl/target/pxa3xx.cfg
+++ b/tcl/target/pxa3xx.cfg
@@ -59,9 +59,9 @@ if { [info exists CPUTAPID_PXA32X_C0] } {
set _CPUTAPID_PXA32X_C0 0x7E642013
}
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
+# set adapter srst delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
+adapter srst delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
diff --git a/tcl/target/qualcomm_qca4531.cfg b/tcl/target/qualcomm_qca4531.cfg
index 3d21578..0b046b8 100644
--- a/tcl/target/qualcomm_qca4531.cfg
+++ b/tcl/target/qualcomm_qca4531.cfg
@@ -38,12 +38,12 @@ reset_config none srst_pulls_trst
# For SRST based variant we still need proper timings.
# For ETH part the reset should be asserted at least for 10ms
# Since there is no other information let's take 100ms to be sure.
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
# according to the SoC documentation it should take at least 5ms from
# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
# to live.
-adapter_nsrst_delay 8
+adapter srst delay 8
if { [info exists CHIPNAME] } {
set _CHIPNAME $_CHIPNAME
diff --git a/tcl/target/readme.txt b/tcl/target/readme.txt
index f028b11..2c3cc8d 100644
--- a/tcl/target/readme.txt
+++ b/tcl/target/readme.txt
@@ -26,12 +26,12 @@ assumed that all write-protect mechanisms should be disabled.
flash write_image [file] <parameters>
verify_image [file] <parameters>
-4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked
+4. adapter speed sets the maximum speed (or alternatively RCLK). If invoked
multiple times only the last setting is used.
interface/xxx.cfg files are always executed *before* target/xxx.cfg
-files, so any adapter_khz in interface/xxx.cfg will be overridden by
-target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively,
+files, so any adapter speed in interface/xxx.cfg will be overridden by
+target/xxx.cfg. adapter speed in interface/xxx.cfg would then, effectively,
set the default JTAG speed.
Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
diff --git a/tcl/target/renesas_s7g2.cfg b/tcl/target/renesas_s7g2.cfg
index 78fb3e8..b4be88f 100644
--- a/tcl/target/renesas_s7g2.cfg
+++ b/tcl/target/renesas_s7g2.cfg
@@ -48,4 +48,4 @@ if { ![using_hla] } {
cortex_m reset_config sysresetreq
}
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg
index 1bc4f2d..2482557 100644
--- a/tcl/target/samsung_s3c2450.cfg
+++ b/tcl/target/samsung_s3c2450.cfg
@@ -7,11 +7,11 @@
#
# RCLK?
#
-# adapter_khz 0
+# adapter speed 0
#
# Really low clock during reset?
#
-# adapter_khz 1
+# adapter speed 1
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg
index 88fe966..9f7c2cd 100644
--- a/tcl/target/samsung_s3c6410.cfg
+++ b/tcl/target/samsung_s3c6410.cfg
@@ -40,7 +40,7 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f \
-expected-id $_C set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
#reset configuration
diff --git a/tcl/target/sim3x.cfg b/tcl/target/sim3x.cfg
index ed46a3b..3d3fc5c 100755
--- a/tcl/target/sim3x.cfg
+++ b/tcl/target/sim3x.cfg
@@ -48,9 +48,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size \
$_WORKAREASIZE set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
diff --git a/tcl/target/smp8634.cfg b/tcl/target/smp8634.cfg
index c13414c..e95f633 100644
--- a/tcl/target/smp8634.cfg
+++ b/tcl/target/smp8634.cfg
@@ -18,7 +18,7 @@ if { [info exists CPUTAPID] } {
set _CPUTAPID 0x08630001
}
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst separate
diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 7fffd2a..fb591c2 100644
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -68,7 +68,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size \
$_WORKAREASIZE # NOTE: this may be increased by a reset-init handler, after it
# configures and enables the PLL. Or you might need to decrease
# this, if you're using a slower clock.
-adapter_khz 500
+adapter speed 500
source [find mem_helper.tcl]
@@ -132,7 +132,7 @@ proc reset_peripherals {family} {
}
$_TARGETNAME configure -event reset-start {
- adapter_khz 500
+ adapter speed 500
#
# When nRST is asserted on most Stellaris devices, it clears some of
diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg
index baac9b6..b20d036 100644
--- a/tcl/target/stm32f0x.cfg
+++ b/tcl/target/stm32f0x.cfg
@@ -52,9 +52,9 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = \
1MHz
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
reset_config srst_nogate
@@ -66,7 +66,7 @@ if {![using_hla]} {
proc stm32f0x_default_reset_start {} {
# Reset clock is HSI (8 MHz)
- adapter_khz 1000
+ adapter speed 1000
}
proc stm32f0x_default_examine_end {} {
@@ -86,7 +86,7 @@ proc stm32f0x_default_reset_init {} {
mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
# Boost JTAG frequency
- adapter_khz 8000
+ adapter speed 8000
}
# Default hooks
diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 471878d..3e85fb2 100644
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -60,9 +60,9 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index 1e8b94a..d790feb 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -28,9 +28,9 @@ if { [info exists WORKAREASIZE] } {
# bit more to be on the safe side. Perhaps superstition, but if are
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 86e9f59..e3f1a34 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -28,9 +28,9 @@ if { [info exists WORKAREASIZE] } {
# bit more to be on the safe side. Perhaps superstition, but if are
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
@@ -73,7 +73,7 @@ if {![using_hla]} {
proc stm32f3x_default_reset_start {} {
# Reset clock is HSI (8 MHz)
- adapter_khz 1000
+ adapter speed 1000
}
proc stm32f3x_default_examine_end {} {
@@ -93,7 +93,7 @@ proc stm32f3x_default_reset_init {} {
mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
# Boost JTAG frequency
- adapter_khz 8000
+ adapter speed 8000
}
# Default hooks
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 09ce14a..b95e783 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -58,9 +58,9 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
# bit more to be on the safe side. Perhaps superstition, but if are
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 2000
+adapter speed 2000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
@@ -100,10 +100,10 @@ $_TARGETNAME configure -event reset-init {
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
# Boost JTAG frequency
- adapter_khz 8000
+ adapter speed 8000
}
$_TARGETNAME configure -event reset-start {
# Reduce speed since CPU speed will slow down to 16MHz with the reset
- adapter_khz 2000
+ adapter speed 2000
}
diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index ba1d12f..db1794c 100755
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -65,9 +65,9 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME \
$_FLASHNAME
# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = \
2MHz
-adapter_khz 2000
+adapter speed 2000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
@@ -162,12 +162,12 @@ $_TARGETNAME configure -event reset-init {
if {[using_jtag]} {
[[target current] cget -dap] memaccess 16
} {
- adapter_khz 8000
+ adapter speed 8000
}
}
$_TARGETNAME configure -event reset-start {
# Reduce speed since CPU speed will slow down to 16MHz with the reset
- adapter_khz 2000
+ adapter speed 2000
}
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 0bfc43d..7296431 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -49,9 +49,9 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
# Clock after reset is HSI at 64 MHz, no need of PLL
-adapter_khz 1800
+adapter speed 1800
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
@@ -108,6 +108,6 @@ $_TARGETNAME configure -event trace-config {
$_TARGETNAME configure -event reset-init {
# Clock after reset is HSI at 64 MHz, no need of PLL
- adapter_khz 4000
+ adapter speed 4000
}
diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index ec5d546..8243fcc 100644
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -24,9 +24,9 @@ if { [info exists WORKAREASIZE] } {
# JTAG speed should be <= F_CPU/6.
# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
-adapter_nsrst_delay 100
+adapter srst delay 100
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
@@ -67,7 +67,7 @@ proc stm32l0_enable_HSI16 {} {
mww 0x4002100c 0x00000001
# Increase speed
- adapter_khz 2500
+ adapter speed 2500
}
$_TARGETNAME configure -event reset-init {
@@ -75,7 +75,7 @@ $_TARGETNAME configure -event reset-init {
}
$_TARGETNAME configure -event reset-start {
- adapter_khz 300
+ adapter speed 300
}
$_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index 054fa9b..a1aeaae 100644
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -23,9 +23,9 @@ if { [info exists WORKAREASIZE] } {
# JTAG speed should be <= F_CPU/6.
# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
@@ -79,7 +79,7 @@ proc stm32l_enable_HSI {} {
mww 0x40023808 0x00000001
# Increase JTAG speed
- adapter_khz 2000
+ adapter speed 2000
}
$_TARGETNAME configure -event reset-init {
@@ -87,7 +87,7 @@ $_TARGETNAME configure -event reset-init {
}
$_TARGETNAME configure -event reset-start {
- adapter_khz 300
+ adapter speed 300
}
$_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index 496b47a..46e6f7e 100644
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -56,9 +56,9 @@ flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
#
# Note that there is a pretty wide band where things are
# more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter_khz 500
+adapter speed 500
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
@@ -78,12 +78,12 @@ $_TARGETNAME configure -event reset-init {
mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
# Boost JTAG frequency
- adapter_khz 4000
+ adapter speed 4000
}
$_TARGETNAME configure -event reset-start {
# Reset clock is MSI (4 MHz)
- adapter_khz 500
+ adapter speed 500
}
$_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm8l.cfg b/tcl/target/stm8l.cfg
index 5cc99e1..386f371 100644
--- a/tcl/target/stm8l.cfg
+++ b/tcl/target/stm8l.cfg
@@ -79,7 +79,7 @@ $_TARGETNAME configure -optionstart $_OPTIONSTART -optionend \
$_OPTIONEND -blocks $_TARGETNAME configure -enable_stm8l
# The khz rate does not apply here, only slow <0> and fast <1>
-adapter_khz 1
+adapter speed 1
reset_config srst_only
diff --git a/tcl/target/stm8s.cfg b/tcl/target/stm8s.cfg
index d55e61b..4768068 100644
--- a/tcl/target/stm8s.cfg
+++ b/tcl/target/stm8s.cfg
@@ -76,7 +76,7 @@ $_TARGETNAME configure -optionstart $_OPTIONSTART -optionend \
$_OPTIONEND -blocks #$_TARGETNAME configure -enable_step_irq
# The khz rate does not apply here, only slow <0> and fast <1>
-adapter_khz 1
+adapter speed 1
reset_config srst_only
diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg
index d26a8b1..29faaaa 100644
--- a/tcl/target/str710.cfg
+++ b/tcl/target/str710.cfg
@@ -1,5 +1,5 @@
#start slow, speed up after reset
-adapter_khz 10
+adapter speed 10
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -29,9 +29,9 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f \
-expected-id $_C set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
$_TARGETNAME configure -event reset-init {
- adapter_khz 6000
+ adapter speed 6000
# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial
diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg
index 48d3134..9a27194 100644
--- a/tcl/target/str730.cfg
+++ b/tcl/target/str730.cfg
@@ -1,6 +1,6 @@
#STR730 CPU
-adapter_khz 3000
+adapter speed 3000
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -27,15 +27,15 @@ reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id \
$_CPUTAPID
#jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
$_TARGETNAME configure -event reset-init {
- adapter_khz 3000
+ adapter speed 3000
# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial
diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg
index ef6e795..335d5ad 100644
--- a/tcl/target/str750.cfg
+++ b/tcl/target/str750.cfg
@@ -19,7 +19,7 @@ if { [info exists CPUTAPID] } {
}
# jtag speed
-adapter_khz 10
+adapter speed 10
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
@@ -29,15 +29,15 @@ reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id \
$_CPUTAPID
#jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
$_TARGETNAME configure -event reset-init {
- adapter_khz 3000
+ adapter speed 3000
init_smi
# Because the hardware cannot be interrogated for the protection state
diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg
index 36c0b2a..7426276 100644
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -13,9 +13,9 @@ if { [info exists ENDIAN] } {
}
# jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
+adapter speed 16
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
@@ -48,11 +48,11 @@ jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 \
-expected-id $_BST set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
- #adapter_khz 3000
+ #adapter speed 3000
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
diff --git a/tcl/target/ti_calypso.cfg b/tcl/target/ti_calypso.cfg
index 9d3b293..52a84fb 100644
--- a/tcl/target/ti_calypso.cfg
+++ b/tcl/target/ti_calypso.cfg
@@ -32,7 +32,7 @@ if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE 0x10000
}
-adapter_khz 1000
+adapter speed 1000
reset_config trst_and_srst
diff --git a/tcl/target/ti_cc26x0.cfg b/tcl/target/ti_cc26x0.cfg
index 7efecb6..8d8a0df 100644
--- a/tcl/target/ti_cc26x0.cfg
+++ b/tcl/target/ti_cc26x0.cfg
@@ -53,4 +53,4 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
diff --git a/tcl/target/ti_cc32xx.cfg b/tcl/target/ti_cc32xx.cfg
index bc3038d..6f91d3f 100644
--- a/tcl/target/ti_cc32xx.cfg
+++ b/tcl/target/ti_cc32xx.cfg
@@ -61,4 +61,4 @@ if { [info exists WORKAREASIZE] } {
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE \
-work-area-backup 0
reset_config srst_only
-adapter_nsrst_delay 1100
+adapter srst delay 1100
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index 4f8f523..91c0087 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -98,8 +98,8 @@ $_TARGETNAME configure \
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index 0db83db..8b52746 100644
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -90,8 +90,8 @@ $_TARGETNAME configure \
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index fa1e6e9..ccc650a 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -70,8 +70,8 @@ $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size \
0x2000 # be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_msp432.cfg b/tcl/target/ti_msp432.cfg
index 3407f75..146e7ee 100644
--- a/tcl/target/ti_msp432.cfg
+++ b/tcl/target/ti_msp432.cfg
@@ -48,4 +48,4 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg
index ce3a176..d06ff97 100644
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti_tms570.cfg
@@ -1,4 +1,4 @@
-adapter_khz 1500
+adapter speed 1500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/tmpa900.cfg b/tcl/target/tmpa900.cfg
index 3ba3591..8e70700 100644
--- a/tcl/target/tmpa900.cfg
+++ b/tcl/target/tmpa900.cfg
@@ -28,7 +28,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_CP
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
-adapter_nsrst_delay 20
+adapter srst delay 20
jtag_ntrst_delay 20
######################
diff --git a/tcl/target/tmpa910.cfg b/tcl/target/tmpa910.cfg
index 5d41c8c..d933c0b 100644
--- a/tcl/target/tmpa910.cfg
+++ b/tcl/target/tmpa910.cfg
@@ -28,7 +28,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_CP
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
-adapter_nsrst_delay 20
+adapter srst delay 20
jtag_ntrst_delay 20
######################
diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index 7ff3929..faaf97d 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -314,7 +314,7 @@ global _MAXSPEED
set _MAXSPEED $MAXSPEED
}
global _MAXSPEED
-adapter_khz $_MAXSPEED
+adapter speed $_MAXSPEED
gdb_breakpoint_override hard
diff --git a/tcl/target/vybrid_vf6xx.cfg b/tcl/target/vybrid_vf6xx.cfg
index 7cb916d..c888d25 100644
--- a/tcl/target/vybrid_vf6xx.cfg
+++ b/tcl/target/vybrid_vf6xx.cfg
@@ -34,4 +34,4 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000
target create ${_TARGETNAME}1 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/xmc1xxx.cfg b/tcl/target/xmc1xxx.cfg
index e693b59..eb94d7b 100644
--- a/tcl/target/xmc1xxx.cfg
+++ b/tcl/target/xmc1xxx.cfg
@@ -38,4 +38,4 @@ $_TARGETNAME configure -work-area-phys 0x20000000 \
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/xmc4xxx.cfg b/tcl/target/xmc4xxx.cfg
index e106d34..3020b28 100644
--- a/tcl/target/xmc4xxx.cfg
+++ b/tcl/target/xmc4xxx.cfg
@@ -57,4 +57,4 @@ if { ![using_hla] } {
cortex_m reset_config sysresetreq
}
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg
index 1562768..b4b6f9f 100644
--- a/tcl/target/zynq_7000.cfg
+++ b/tcl/target/zynq_7000.cfg
@@ -23,7 +23,7 @@ target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
-coreid 1 -dbgbase 0x80092000
target smp ${_TARGETNAME}0 ${_TARGETNAME}1
-adapter_khz 1000
+adapter speed 1000
${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
diff --git "a/tcl/target/\320\2721879x\320\2611\321\217.cfg" \
"b/tcl/target/\320\2721879x\320\2611\321\217.cfg" index 7d8c113..0a8467f 100644
--- "a/tcl/target/\320\2721879x\320\2611\321\217.cfg"
+++ "b/tcl/target/\320\2721879x\320\2611\321\217.cfg"
@@ -1,7 +1,7 @@
# СБИС К1879ХБ1Я
# http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/
-adapter_khz 1000
+adapter speed 1000
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/test/syntax1.cfg b/tcl/test/syntax1.cfg
index 79d5384..e23cfaf 100644
--- a/tcl/test/syntax1.cfg
+++ b/tcl/test/syntax1.cfg
@@ -1,4 +1,4 @@
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
#use combined on interfaces or targets that can't set TRST/SRST separately
diff --git a/tcl/tools/firmware-recovery.tcl b/tcl/tools/firmware-recovery.tcl
index 8e017ce..8b28656 100644
--- a/tcl/tools/firmware-recovery.tcl
+++ b/tcl/tools/firmware-recovery.tcl
@@ -29,7 +29,7 @@ dump_part <name> <filename> save partition's contents to a file
erase_part <name> erase the given partition
flash_part <name> <filename> erase, flash and verify the given partition
ram_boot <filename> load binary file to RAM and run it
-adapter_khz <freq> set JTAG clock frequency in kHz
+adapter speed <freq> set JTAG clock frequency in kHz
For example, to clear nvram and reflash CFE on an RT-N16 using TUMPA, run:
openocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \\
@@ -39,7 +39,7 @@ openocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \
\\ }
# set default, can be overriden later
-adapter_khz 1000
+adapter speed 1000
proc get_partition { name } {
global partition_list
--
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