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List:       openocd-development
Subject:    [OpenOCD-devel] [PATCH]: 22723f7 tcl/target/stm32f7x: configure faster system clock in reset-init
From:       gerrit () openocd ! org (gerrit)
Date:       2018-03-12 22:51:01
Message-ID: 20180312225101.B7C7C2522927 () mail ! openocd ! org
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This is an automated email from Gerrit.

Tomas Vanek (vanekt@fbl.cz) just uploaded a new patch set to Gerrit, which you can \
find at http://openocd.zylin.com/4464

-- gerrit

commit 22723f76148c57dc5655b85df829ac6af3fb61f8
Author: Tomas Vanek <vanekt@fbl.cz>
Date:   Mon Mar 12 23:42:23 2018 +0100

    tcl/target/stm32f7x: configure faster system clock in reset-init
    
    STM32F7xx devices need faster clock for flash programming
    over JTAG transport. Using reset default 16 MHz clock
    resulted in lot of DAP WAITs and substantial decrease
    of flashing performance.
    
    Change-Id: Ida6915331dd924c9c0d08822fd94c04ad408cdc5
    Signed-off-by: Tomas Vanek <vanekt@fbl.cz>

diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index 4065e2a..1f36bb4 100755
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -81,3 +81,21 @@ $_TARGETNAME configure -event trace-config {
 	# assignment
 	mmw 0xE0042004 0x00000020 0
 }
+
+$_TARGETNAME configure -event reset-init {
+	# Configure PLL to boost clock to HSI x 8 (128 MHz)
+	mww 0x40023804 0x08002008   ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /2(P)
+	mww 0x40023C00 0x00000106   ;# FLASH_ACR = PRFTBE | 6(Latency)
+	mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
+	mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
+
+	# Boost JTAG frequency
+	adapter_khz 8000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reduce speed since CPU speed will slow down to 16MHz with the reset
+	adapter_khz 2000
+}

-- 

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