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List:       openocd-development
Subject:    [OpenOCD-devel] [PATCH]: 97a5119 cortex_a: unlock OS Lock without need to check part number
From:       gerrit () openocd ! org (gerrit)
Date:       2015-11-29 22:23:50
Message-ID: 20151129222350.D44AA19808D7 () mail ! openocd ! org
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This is an automated email from Gerrit.

Jiri Kastner (cz172638@gmail.com) just uploaded a new patch set to Gerrit, which you \
can find at http://openocd.zylin.com/3137

-- gerrit

commit 97a51190d9dedd335024b001a9954c60147e5456
Author: Jiri Kastner <cz172638@gmail.com>
Date:   Sun Nov 29 22:34:41 2015 +0100

    cortex_a: unlock OS Lock without need to check part number
    
    unlocking based on partnumber makes code complicated.
    tested on cortex a15, snapdragon, cortex a8
    
    Change-Id: Ie7dd47c112032c365de87eff64d68251fe2a3fc8
    Signed-off-by: Jiri Kastner <cz172638@gmail.com>

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index e2d433a..2f69de7 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -172,9 +172,27 @@ static int cortex_a8_init_debug_access(struct target *target)
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct adiv5_dap *swjdp = armv7a->arm.dap;
 	int retval;
+	uint32_t dbg_osreg;
 
 	LOG_DEBUG(" ");
 
+	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+						    armv7a->debug_base + CPUDBG_OSLSR,
+						    &dbg_osreg);
+	if (retval != ERROR_OK)
+		return retval;
+	LOG_DEBUG("DBGOSLSR  0x%" PRIx32, dbg_osreg);
+
+	if (dbg_osreg & CPUDBG_OSLAR_LK_MASK)
+		/* Unlocking the DEBUG OS registers for modification */
+		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+							     armv7a->debug_base + CPUDBG_OSLAR,
+							     0);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+
 	/* Unlocking the debug registers for modification
 	 * The debugport might be uninitialised so try twice */
 	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
@@ -2920,8 +2938,8 @@ static int cortex_a_examine_first(struct target *target)
 	} else
 		armv7a->debug_base = target->dbgbase;
 
-	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
-			armv7a->debug_base + CPUDBG_CPUID, &cpuid);
+	retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+			   armv7a->debug_base + CPUDBG_OSLAR, 0);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -2963,30 +2981,6 @@ static int cortex_a_examine_first(struct target *target)
 	cortex_a->ttypr = ttypr;
 	cortex_a->didr = didr;
 
-	/* Unlocking the debug registers */
-	if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
-		CORTEX_A15_PARTNUM) {
-
-		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
-						     armv7a->debug_base + CPUDBG_OSLAR,
-						     0);
-
-		if (retval != ERROR_OK)
-			return retval;
-
-	}
-	/* Unlocking the debug registers */
-	if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
-		CORTEX_A7_PARTNUM) {
-
-		retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
-						     armv7a->debug_base + CPUDBG_OSLAR,
-						     0);
-
-		if (retval != ERROR_OK)
-			return retval;
-
-	}
 	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 					    armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
 

-- 

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