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List: openocd-development
Subject: [OpenOCD-devel] [PATCH]: 84008c9 tcl: add support for NXP LPC15XX family and add target configuratio
From: gerrit () openocd ! org (gerrit)
Date: 2015-08-23 16:19:19
Message-ID: 20150823161919.25C7219807C9 () mail ! openocd ! org
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This is an automated email from Gerrit.
Jean-François Wauthy (jfw@spancircle.be) just uploaded a new patch set to Gerrit, \
which you can find at http://openocd.zylin.com/2943
-- gerrit
commit 84008c9e58a57ccd22e464ed2b01908cc9eba726
Author: Jean-François Wauthy <jfw@spancircle.be>
Date: Sun Aug 23 18:07:29 2015 +0200
tcl: add support for NXP LPC15XX family and add target configuration file
for the LPC1549
The current auto mode for lpc2000 flash does not work with the lpc1500 variant,
CHIPROMSIZE must therefore be defined before including target/lpc1xxx.cfg.
Tested on a NXP OM13056 demo board with an Olimex ARM-USB-OCD-H in SWD mode.
Change-Id: I1b27029c2d59356f7be73a3a56a56de2d0ea2520
Signed-off-by: Jean-François Wauthy <jfw@spancircle.be>
diff --git a/tcl/target/lpc1549.cfg b/tcl/target/lpc1549.cfg
new file mode 100644
index 0000000..3707b60
--- /dev/null
+++ b/tcl/target/lpc1549.cfg
@@ -0,0 +1,6 @@
+# NXP LPC1549 Cortex-M3 with 36kB of SRAM and 256 kB of Flash
+set CHIPNAME lpc1549
+set CHIPROMSIZE 0x40000
+set WORKAREASIZE 0x9000
+
+source [find target/lpc15xx.cfg]
diff --git a/tcl/target/lpc15xx.cfg b/tcl/target/lpc15xx.cfg
new file mode 100644
index 0000000..206ca04
--- /dev/null
+++ b/tcl/target/lpc15xx.cfg
@@ -0,0 +1,11 @@
+# NXP LPC15xx Cortex-M3 with at least 12kB SRAM
+if { ![info exists CHIPNAME] } {
+ set CHIPNAME lpc15xx
+}
+
+set CHIPSERIES lpc1500
+if { ![info exists WORKAREASIZE] } {
+ set WORKAREASIZE 0x3000
+}
+
+source [find target/lpc1xxx.cfg]
diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg
index 226425d..c239829 100644
--- a/tcl/target/lpc1xxx.cfg
+++ b/tcl/target/lpc1xxx.cfg
@@ -3,8 +3,8 @@
# !!!!!!
#
# This file should not be included directly, rather by the lpc11xx.cfg,
-# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
-# appropriate values.
+# lpc13xx.cfg, lpc15xx.cfg, lpc17xx.cfg, etc. which set the needed variables
+# to the appropriate values.
#
# !!!!!!
@@ -13,6 +13,7 @@
# LPC12xx chips support only SWD transport.
# LPC11Uxx chips support only SWD transports.
# LPC13xx chips support only SWD transports.
+# LPC15xx chips support only SWD transports.
# LPC17xx chips support both JTAG and SWD transports.
# LPC40xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
@@ -21,17 +22,17 @@ source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
- error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the \
specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)." \
+ error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the \
specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc15xx.cfg, lpc17xx.cfg, \
etc)." }
if { [info exists CHIPSERIES] } {
# Validate chip series is supported
- if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != \
"lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != \
"lpc4000" } { + if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && \
$CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1500" && \
$CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } { error "Unsupported LPC1xxx \
chip series specified." }
set _CHIPSERIES $CHIPSERIES
} else {
- error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the \
specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)." \
+ error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the \
specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc15xx.cfg, lpc17xx.cfg, \
etc)." }
# After reset, the chip is clocked by an internal RC oscillator.
@@ -44,8 +45,8 @@ if { [info exists CCLK] } {
# Allow user override
set _CCLK $CCLK
} else {
- # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except \
for LPC177x/8x,LPC407x/8x)
- if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == \
"lpc1200" || $_CHIPSERIES == "lpc1300" } { + # LPC8xx/LPC11xx/LPC12xx/LPC13xx/LPC15xx \
use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x) + if { \
$_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || \
$_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1500" } { set _CCLK 12000
} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
set _CCLK 4000
@@ -56,10 +57,10 @@ if { [info exists CPUTAPID] } {
# Allow user override
set _CPUTAPID $CPUTAPID
} else {
- # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 \
core,LPC40xx use a Cortex-M4F core. + # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ \
core, LPC13xx/LPC15xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core. if \
{ $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" \
} { set _CPUTAPID 0x0bb11477
- } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES \
== "lpc4000" } { + } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1500" \
|| $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { if { [using_jtag] } {
set _CPUTAPID 0x4ba00477
} {
@@ -79,29 +80,47 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at \
0x10000000)
-# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
-# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at \
0x10000000)
-# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
-# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at \
0x10000000)
-# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at \
0x10000000)
-$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
+if { $_CHIPSERIES == "lpc1500" } {
+ # The LPC15xx devices have 12/20/36kB of SRAM in the ARMv7-M "Code" area (at \
0x02000000) + $_TARGETNAME configure -work-area-phys 0x02000000 -work-area-size \
$_WORKAREASIZE +} else {
+ # The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at \
0x10000000) + # The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area \
(at 0x10000000) + # The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" \
area (at 0x10000000) + # The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M \
"Code" area (at 0x10000000) + # The LPC17xx devices have 8/16/32/64kB of SRAM in the \
ARMv7-M "Code" area (at 0x10000000) + # The LPC40xx devices have 16/32/64kB of SRAM \
in the ARMv7-ME "Code" area (at 0x10000000) + $_TARGETNAME configure -work-area-phys \
0x10000000 -work-area-size $_WORKAREASIZE +}
-# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
-# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
-# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at \
0x00000000)
-# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
-# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
-# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
+# The LPC11xx devices have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
+# The LPC12xx devices have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
+# The LPC11Uxx devices have 16/24/32/40/48/64/96/128kB of flash memory (at \
0x00000000) +# The LPC13xx devices have 8/16/32kB of flash memory (at 0x00000000)
+# The LPC15xx devices have 64/128/256kB of flash memory (at 0x00000000)
+# The LPC17xx devices have 32/64/128/256/512kB of flash memory (at 0x00000000)
+# The LPC40xx devices have 64/128/256/512kB of flash memory (at 0x00000000)
#
# All are compatible with the "lpc1700" variant of the LPC2000 flash driver
# (same cmd51 destination boundary alignment, and all three support 256 byte
# transfers).
#
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc \
checksum]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
- auto $_CCLK calc_checksum
+if { $_CHIPSERIES == "lpc1500" } {
+ if { [info exists CHIPROMSIZE] } {
+ set _CHIPROMSIZE $CHIPROMSIZE
+ } else {
+ error "CHIPROMSIZE is not set. The $CHIPNAME part is available in several Flash \
size configurations and cannot be detected automatically. Please set CHIPROMSIZE." + \
} +
+ set _FLASHNAME $_CHIPNAME.flash
+ flash bank $_FLASHNAME lpc2000 0x0 $_CHIPROMSIZE 0 0 $_TARGETNAME \
+ lpc1500 $_CCLK calc_checksum
+} else {
+ set _FLASHNAME $_CHIPNAME.flash
+ flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
+ auto $_CCLK calc_checksum
+}
if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == \
"lpc1200" || $_CHIPSERIES == "lpc1300" } { # Do not remap 0x0000-0x0200 to anything \
but the flash (i.e. select @@ -118,6 +137,21 @@ if { $_CHIPSERIES == "lpc800" || \
$_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "l $_TARGETNAME configure -event \
reset-init { mww 0x40048000 0x02
}
+} elseif { $_CHIPSERIES == "lpc1500" } {
+ # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
+ # "User Flash Mode" where interrupt vectors are _not_ remapped,
+ # and reside in flash instead).
+ #
+ # Table 8. System memory remap register (SYSMEMREMAP, address 0x4007 4000) bit \
description + # Bit Symbol Value Description
+ # 1:0 MAP System memory remap
+ # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
+ # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
+ # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside \
in Flash. + # 31:2 - - Reserved.
+ $_TARGETNAME configure -event reset-init {
+ mww 0x40074000 0x02
+ }
} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
@@ -150,7 +184,7 @@ if {[using_jtag]} {
# LPC8xx (Cortex M0+ core) support SYSRESETREQ
# LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ
-# LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ
+# LPC13xx/LPC15xx/LPC17xx (Cortex M3 core) support SYSRESETREQ
# LPC40xx (Cortex M4F core) support SYSRESETREQ
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
--
------------------------------------------------------------------------------
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