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List: openocd-development
Subject: [OpenOCD-devel] [PATCH]: 9e23158 Fix printf format specifiers errors exposed by arm-none-eabi build
From: gerrit () openocd ! zylin ! com
Date: 2015-03-30 7:55:48
Message-ID: 20150330075548.67F1E242EB () openocd ! zylin ! com
[Download RAW message or body]
This is an automated email from Gerrit.
Paul Fertser (fercerpav@gmail.com) just uploaded a new patch set to Gerrit, which you \
can find at http://openocd.zylin.com/2664
-- gerrit
commit 9e23158fc7ba3572befc4315306d370d6dd7c3c6
Author: Paul Fertser <fercerpav@gmail.com>
Date: Mon Mar 30 10:47:31 2015 +0300
Fix printf format specifiers errors exposed by arm-none-eabi build
Change-Id: I0489991866fce0bd2e1d00c0bc14fdd17bde4726
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index de0f1cc..4de5826 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -976,8 +976,8 @@ COMMAND_HANDLER(samd_handle_bootloader_command)
nb = (2 << (8 - size)) * page_size;
/* There are 4 pages per row */
- command_print(CMD_CTX, "Bootloader size is %u bytes (%u rows)",
- nb, nb / (page_size * 4));
+ command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%u rows)",
+ nb, (unsigned int)(nb / (page_size * 4)));
}
}
}
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index c2a1fc2..0b511b0 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -1478,7 +1478,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
break;
default:
- LOG_ERROR("BUG: unknown Part ID encountered: 0x%x", part_id);
+ LOG_ERROR("BUG: unknown Part ID encountered: 0x%" PRIx32, part_id);
exit(-1);
}
@@ -1500,7 +1500,7 @@ static int lpc2000_probe(struct flash_bank *bank)
status = get_lpc2000_part_id(bank, &part_id);
if (status == LPC2000_CMD_SUCCESS)
LOG_INFO("If auto-detection fails for this part, please email "
- "openocd-devel@lists.sourceforge.net, citing part id 0x%x.\n", part_id);
+ "openocd-devel@lists.sourceforge.net, citing part id 0x%" PRIx32 ".", part_id);
}
lpc2000_build_sector_list(bank);
diff --git a/src/flash/nor/nrf51.c b/src/flash/nor/nrf51.c
index 34297ef..351a86e 100644
--- a/src/flash/nor/nrf51.c
+++ b/src/flash/nor/nrf51.c
@@ -709,7 +709,7 @@ static int nrf51_erase_page(struct flash_bank *bank,
LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
if (sector->is_protected) {
- LOG_ERROR("Cannot erase protected sector at 0x%x", sector->offset);
+ LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
return ERROR_FAIL;
}
diff --git a/src/flash/nor/sim3x.c b/src/flash/nor/sim3x.c
index 867d0ca..5a722df 100644
--- a/src/flash/nor/sim3x.c
+++ b/src/flash/nor/sim3x.c
@@ -512,7 +512,7 @@ static int sim3x_flash_write(struct flash_bank *bank, const \
uint8_t * buffer, ui "for padding buffer");
return ERROR_FAIL;
}
- LOG_INFO("odd number of bytes to write (%d), extending to %d "
+ LOG_INFO("odd number of bytes to write (%" PRId32 "), extending to %" PRId32 " "
"and padding with 0xff", old_count, count);
new_buffer[count - 1] = 0xff;
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 27b6632..d1ea424 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -507,12 +507,12 @@ static int get_stellaris_info(struct flash_bank *bank, char \
*buf, int buf_size) printed = snprintf(buf,
buf_size,
"did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
- ", eproc: %s, ramsize: %ik, flashsize: %ik\n",
+ ", eproc: %s, ramsize: %" PRIu32 "k, flashsize: %uk\n",
stellaris_info->did1,
stellaris_info->did1,
"ARMv7M",
stellaris_info->sramsiz,
- stellaris_info->num_pages * stellaris_info->pagesize / 1024);
+ (unsigned int)(stellaris_info->num_pages * stellaris_info->pagesize / 1024));
buf += printed;
buf_size -= printed;
diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c
index bbb96b2..a86f1f4 100644
--- a/src/rtos/mqx.c
+++ b/src/rtos/mqx.c
@@ -138,12 +138,12 @@ static int mqx_target_read_buffer(
{
int status = mqx_valid_address_check(target->rtos, address);
if (status != ERROR_OK) {
- LOG_WARNING("MQX RTOS - target address 0x%X is not allowed to read", address);
+ LOG_WARNING("MQX RTOS - target address 0x%" PRIX32 " is not allowed to read", \
address); return status;
}
status = target_read_buffer(target, address, size, buffer);
if (status != ERROR_OK) {
- LOG_ERROR("MQX RTOS - reading target address 0x%X failed", address);
+ LOG_ERROR("MQX RTOS - reading target address 0x%" PRIX32 " failed", address);
return status;
}
return ERROR_OK;
@@ -181,7 +181,8 @@ static int mqx_get_member(
rtos->target, base_address + member_offset, member_width, result
);
if (status != ERROR_OK)
- LOG_WARNING("MQX RTOS - cannot read \"%s\" at address 0x%X", member_name, \
base_address + member_offset); + LOG_WARNING("MQX RTOS - cannot read \"%s\" at \
address 0x%" PRIX32, + member_name, (uint32_t)(base_address + member_offset));
return status;
}
@@ -435,7 +436,7 @@ static int mqx_update_threads(
if (NULL == rtos->thread_details[i].extra_info_str)
return ERROR_FAIL;
snprintf(
- rtos->thread_details[i].extra_info_str, extra_info_length, "%s : 0x%x : %u",
+ rtos->thread_details[i].extra_info_str, extra_info_length, "%s : 0x%" PRIx32 " : \
%" PRIu32, state_name, task_addr, task_errno
);
/* set active thread */
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 4f19e95..c09d4ec 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1364,7 +1364,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
full = "(Debug Unit)";
break;
default:
- LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
+ LOG_DEBUG("Unrecognized Part number 0x%u", part_num);
type = "-*- unrecognized -*-";
full = "";
break;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 9ae0432..a8db8f8 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -238,7 +238,7 @@ static int cortex_a_init_debug_access(struct target *target)
the registers in the Core Power Domain */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
- LOG_DEBUG("target->coreid %d DBGPRSR 0x%x ", target->coreid, dbg_osreg);
+ LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, \
dbg_osreg);
if (retval != ERROR_OK)
return retval;
@@ -2951,7 +2951,7 @@ static int cortex_a_examine_first(struct target *target)
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("target->coreid %d DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg);
+ LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, \
dbg_osreg);
armv7a->arm.core_type = ARM_MODE_MON;
retval = cortex_a_dpm_setup(cortex_a, didr);
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index f6cd451..cf6f697 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -352,9 +352,9 @@ static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info)
EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB",
EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB",
EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB");
- LOG_DEBUG("EJTAG v2.0: Break Channels: %i",
- (ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
- EJTAG_V20_IMP_BCHANNELS_MASK);
+ LOG_DEBUG("EJTAG v2.0: Break Channels: %u",
+ (unsigned int)((ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
+ EJTAG_V20_IMP_BCHANNELS_MASK));
}
static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info)
--
------------------------------------------------------------------------------
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