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List:       openocd-development
Subject:    [Openocd-development] jlink issues
From:       openwrt () marshadder ! org (Peter Denison)
Date:       2009-05-31 9:14:46
Message-ID: Pine.LNX.4.64.0905310922320.10911 () marshadder ! org
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On Sat, 30 May 2009, Peter Denison wrote:

> On Sat, 30 May 2009, Magnus Lundin wrote:
>
>> It looks like you are using  jtag_khz  0, this  means adaptive clocking with
>> the RTCK signal. This work for LPC3148 that has a RTCK signal, but as far as
>> I can find there is no RTCK singal on the  TMS470R1A256.
>>
>> For testing  interface problem I would suggest, always start with a slow jtag
>> clock, like jtag_khz 30 or 100. If this works try to increase it.
>
> Many thanks! Somehow in my testing (probably to try to replicate XC's
> config) I had put jtag_rclk in my .cfg file.
>
> I've replaced it with jtag_khz 30, and I can at least initialise now.
> Sorry for the misdirection.
>
> So, summary: r1932, J-Link V6, XScale IXP422 target. Initialisation works.

Only it doesn't reliably! This adapter is driving me up the wall.

The first time after power-up, the adapter fails on the first 
EMU_CMD_HW_JTAG3 if it's 7 bits (0x7F) long, and works if it's 8 bits 
(0xFF) long.

By failure, I mean that the adapter simply fails to respond to the 
command, and the USB layer times out.

However, after it has worked once, any size bit sequences work.

I suppose I could put in a "first time" flag so that the first (RESET -> 
RESET) transition is always 8 bits. Thoughts?

J-Link ARM V6 compiled Mar  3 2008 18:04:42


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