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List:       openocd-development
Subject:    [Openocd-development] Delay beforte jtag verification for
From:       Dominic.Rath () gmx ! de (Dominic Rath)
Date:       2006-11-22 16:37:36
Message-ID: 200611221737.36410.Dominic.Rath () gmx ! de
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Hello Magnus,

do you know why your interface pulls reset low when you launch the OpenOCD?

Instead of adding a delay, or waiting for the chain validation to succeed, we 
could add a means of telling the OpenOCD that reset got asserted on startup - 
there's already code for delaying after a reset (jtag_n[st]rst_delay).

Regards,

Dominic

On Tuesday 21 November 2006 13:20, Magnus Lundin wrote:
> Hello
>
> I have problems connecting openocd to a Stellaris Cortex processor using
> a different JTAG interface than the one embedded on the 811 evalutaion
> board.
> The problem is that the processor has a 30ms startup period after reset
> low is released.
>
> My FTDI jtag interface lowers the reset line on USB reset, happens
> wenever OpenOCD is restarted, initializes the  MPSSE mode and then tries
> to verify  the JTAG  connection. This fails because the processor has
> not yet started up. So I have to add a 30-40ms delay between jtag
> interface initialisation and verification of jtag communication.
>
> The reason the evaluation board works is that there is an active high
> jtagenable signal that works as a reset enable and keeps the
> uninitilised ftdi2232 from driving reset low.
>
> This can be made into yet another configuration option or we can
> increase the startup time of OpenOCD by 40ms.
>
> Comments ?
>
> Regards,
>
> Magnus
>
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